Commits · fba1f36d138cd50eb313d77cd538724f09287214 · Roger Ferrer / llvm-epi · GitLab

Nov 08, 2021
- [Test][SCCP] Precommit tests for PR52253 · fba1f36d
  Anton Afanasyev authored Oct 24, 2021
  
  fba1f36d
- [Test][SCCP] Update autogenerated test before precommit · 21186233
  Anton Afanasyev authored Oct 28, 2021
  
  21186233
- [SVE][CodeGen] Improve codegen for some FP insert_subvector cases · 8d38c24f
  David Sherwood authored Nov 05, 2021
  8d38c24f
- Revert "[IndVars] Pass TTI to replaceCongruentIVs" · 8d4eba6c
  Dmitry Makogon authored Nov 08, 2021
  8d4eba6c
- [AArch64][SVE] Combine FADD and FMUL aarch64 intrinsics to FMLA · 4a59694b
  Matt authored Nov 03, 2021
  4a59694b
- [IndVars] Pass TTI to replaceCongruentIVs · db289340
  Dmitry Makogon authored Nov 02, 2021
  db289340
- [AArch64] Precommit i256 test from D111530 · 1f60302a
  Simon Pilgrim authored Nov 08, 2021
  
  1f60302a
- [AArch64] Combine fptoi.sat(fmul) to fixed point cvtf · a982940e
  David Green authored Nov 08, 2021
  a982940e
- [LoopVectorize] Permit fixed-width epilogue loops for scalable vector bodies · c42bb30b
  David Sherwood authored Sep 07, 2021
  c42bb30b
- [PowerPC] Implement basic macro fusion in Power10 · 9b5e2b52
  Qiu Chaofan authored Nov 08, 2021
  9b5e2b52
- [AArch64] Canonicalize X*(Y+1) or X*(1-Y) to madd/msub · bf3784b8
  Andrew Wei authored Nov 08, 2021
  bf3784b8
- [XCOFF][llvm-readobj] improve the relocation output. · 9b6f264d
  Esme-Yi authored Nov 08, 2021
  9b6f264d
- [RISCV] Optimize (add (mul r, c0), c1) · e32cf690
  Ben Shi authored Oct 05, 2021
  e32cf690
- [CSKY] Add CSKY 16-bit instruction format and encoding · 4fb282fe
  Zi Xuan Wu authored Nov 08, 2021
  4fb282fe
- [AsmPrinter][ORE] use correct opcode name · 50acbbe3
  Chen Zheng authored Nov 04, 2021
  50acbbe3
- [ORE][AsmPrinter] add testcase for D113173; NFC · c7d27f90
  Chen Zheng authored Nov 04, 2021
  
  c7d27f90
Nov 07, 2021
- [X86][AVX2] Recognise 256-bit truncation shuffles and mask 256-bit source · 55e4cd84
  Simon Pilgrim authored Nov 07, 2021
  55e4cd84
- [AArch64] Rewrite and update fcvt-fixed.ll. NFC · 17acd6d9
  David Green authored Nov 07, 2021
  17acd6d9
- [BasicAA] Use index size instead of pointer size · a8c318b5
  Nikita Popov authored Oct 23, 2021
  a8c318b5
- [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC · d391e4fe
  Simon Pilgrim authored Nov 07, 2021
  d391e4fe
- [X86][AVX] Add missing X86ISD::VBROADCAST(v4f32 -> v8f32) isel pattern for AVX1 targets · b5ef56f0
  Simon Pilgrim authored Nov 07, 2021
  b5ef56f0
- [X86] Add AVX512 test coverage to vselect-zero.ll · f7880a78
  Simon Pilgrim authored Nov 07, 2021
  f7880a78
Nov 06, 2021
- [InstSimplify] Remove incorrect icmp of gep fold (PR52429) · e3cec17b
  Nikita Popov authored Nov 06, 2021
  e3cec17b
- [NFC][X86][Costmodel] Add tests for i32/i64 replication shuffles · 23566f18
  Roman Lebedev authored Nov 06, 2021
  23566f18
- [Test][SLPVectorizer] Precommit test for PR52275 · 1c2ad70f
  Anton Afanasyev authored Nov 06, 2021
  
  1c2ad70f
- [TTI][CostModel] `getUserCost()`: recognize replication shuffles and query their cost · a30ec477
  Roman Lebedev authored Nov 06, 2021
  a30ec477
- [InstCombine] match usub.sat from umax intrinsic · 83c2fb9f
  Sanjay Patel authored Nov 05, 2021
  83c2fb9f
- [InstCombine] add tests for umax with sub; NFC · 025a2f73
  Sanjay Patel authored Nov 05, 2021
  
  025a2f73
- DebugInfo: Simplified Template Names: drop unneeded space in arrays · 0a5c26f2
  David Blaikie authored Nov 05, 2021
  0a5c26f2
- [llvm-profgen] Fix index out of bounds error while using ip.advance · 5bf191a3
  wlei authored Nov 04, 2021
  5bf191a3
Nov 05, 2021
- DWARF Simplified Template Names: Narrow down the handling for operator overloads · f57d0e27
  David Blaikie authored Nov 05, 2021
  f57d0e27
- [SCEV] Use constant range of RHS to prove NUW on narrow IV in trip count logic · d24a0e88
  Philip Reames authored Nov 05, 2021
  d24a0e88
- [NFC][CostModel] Add exhaustive test coverage for replication shuffles · 04fa7cbf
  Roman Lebedev authored Nov 06, 2021
  04fa7cbf
- [TwoAddressInstructionPass] Update existing physreg live intervals · bdaa1810
  Jay Foad authored Nov 04, 2021
  bdaa1810
- Autogen tests for ease of future update · e69f6476
  Philip Reames authored Nov 05, 2021
  
  e69f6476
- [DAGCombiner] add fold for vselect based on mask of signbit, part 2 · 7e30404c
  Sanjay Patel authored Nov 05, 2021
  7e30404c
- [AArch] add tests for vselect; NFC · 4d513f25
  Sanjay Patel authored Nov 05, 2021
  4d513f25
- [x86] add tests for vector select; NFC · fc852462
  Sanjay Patel authored Nov 05, 2021
  
  fc852462
- Reland "[Attr] support btf_type_tag attribute" · 3466e007
  Yonghong Song authored Nov 05, 2021
  3466e007
- [AArch64][GISel] Optimize 8 and 16 bit variants of uaddo. · f64580f8
  Florian Hahn authored Nov 05, 2021
  f64580f8