Commits · fcd0cb39214e5abc89bfb1926397fe668172ecaa · Roger Ferrer / llvm-epi · GitLab

Jun 30, 2021
- Fix MSVC "32-bit shift implicitly converted to 64 bits" warning. · fcd0cb39
  Simon Pilgrim authored Jun 30, 2021
  
  fcd0cb39
- [AMDGPU] Simplify getReservedNumSGPRs · a7ed55f6
  madhur13490 authored Jun 18, 2021
  a7ed55f6
- [MTE] Remove redundant helper function. · a24f1046
  Florian Mayer authored Jun 29, 2021
  a24f1046
- [ARMInstPrinter] Print the target address of a branch instruction · 657e067b
  Igor Kudrin authored Jun 30, 2021
  657e067b
- [ARM][NFC] Remove an unused method · 17bcae89
  Igor Kudrin authored Jun 30, 2021
  17bcae89
- Recommit "[AArch64] Custom lower <4 x i8> loads" · b062fff8
  Sjoerd Meijer authored Jun 29, 2021
  b062fff8
- [AMDGPU] Update gfx90a memory model support · 7f19aa73
  Tony Tye authored May 07, 2021
  7f19aa73
- [Clang][NVPTX] Add NVPTX intrinsics and builtins for CUDA PTX 6.5 and 7.0 WMMA and MMA instructions · 3644726a
  Steffen Larsen authored Jun 28, 2021
  3644726a
Jun 29, 2021
- CodeGen: Store LLT instead of uint64_t in MachineMemOperand · 990278d0
  Matt Arsenault authored May 19, 2021
  990278d0
- [RISCV] Protect the SHL/SRA/SRL handlers in LowerOperation against being... · 3b6dfa38
  Craig Topper authored Jun 28, 2021
  3b6dfa38
- [AMDGPU] Fix 224-bit spills · f38a8b54
  Piotr Sobczak authored Jun 29, 2021
  f38a8b54
- [SVE] Added CodeGen support for inserting an element into a predicate vector · c3d3defd
  Dylan Fleming authored Jun 29, 2021
  c3d3defd
- [AVR] Fix a bug in prologue of ISR · c85175c5
  Ben Shi authored Jun 29, 2021
  c85175c5
- ARM: fix vacuously true assertion to actually check what it should. NFC. · c82957e7
  Tim Northover authored Jun 29, 2021
  
  c82957e7
- [ARM] Fold extract of ARM_BUILD_VECTOR · 371ee32e
  David Green authored Jun 29, 2021
  371ee32e
Jun 28, 2021
- [Hexagon] Add patterns to load i1 · 9c5ed8d5
  Krzysztof Parzyszek authored Jun 25, 2021
  9c5ed8d5
- Revert "[AArch64] Custom lower <4 x i8> loads" · 3a7cea28
  Sjoerd Meijer authored Jun 28, 2021
  3a7cea28
- [AMDGPU] Use opName instead of PseudoName in VOP2 multiclasses. NFC. · 75cacc67
  Jay Foad authored Jun 28, 2021
  75cacc67
- [llvm][ARM] Treat xscale arch as an alias of armv5te · 558d9e82
  David Spickett authored Jun 23, 2021
  558d9e82
- [AArch64][SVE] DAG combine SETCC_MERGE_ZERO of a SETCC_MERGE_ZERO · c089e29a
  Bradley Smith authored Jun 25, 2021
  c089e29a
- [AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX · f9f5d415
  Brendon Cahoon authored Apr 30, 2021
  f9f5d415
- [Aarch64] Adding support for Armv9-A Realm Management Extension · 88b1135e
  Lucas Prates authored Jun 22, 2021
  88b1135e
- [ARM] Add an extra fold for f32 extract(vdup(i32)) · a1c0f09a
  David Green authored Jun 28, 2021
  a1c0f09a
- Revert "[M68k][GloballSel] Formal arguments lowering in IRTranslator" · 04242bdc
  Min Hsu authored Jun 27, 2021
  04242bdc
- [M68k][GloballSel] Formal arguments lowering in IRTranslator · 8f43407a
  Sushma Unnibhavi authored Jun 27, 2021
  8f43407a
Jun 27, 2021
- Revert "[RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve... · 010f0f00
  Craig Topper authored Jun 27, 2021
  010f0f00
- [X86] Tighten up some inline assembly constraint handling. · 81f6d7c0
  Craig Topper authored Jun 26, 2021
  81f6d7c0
Jun 26, 2021
- [ARM] Lower MVETRUNC to stack operations · 41d8149e
  David Green authored Jun 26, 2021
  41d8149e
- [ARM] Introduce MVETRUNC ISel lowering · 59558129
  David Green authored Jun 26, 2021
  59558129
- [RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve usage of those instructions. · 81b2f959
  Craig Topper authored Jun 26, 2021
  
  81b2f959
- [ARM] MVE vabd · 0f83d37a
  David Green authored Jun 26, 2021
  0f83d37a
- [ISel] Port AArch64 SABD and UABD to DAGCombine · 2887f146
  David Green authored Jun 26, 2021
  2887f146
- [RISCV][NFC] Combine the control flow for different RetOp of interrupt function · 779d2b0a
  Jim Lin authored Jun 26, 2021
  779d2b0a
- [RISCV] Add DAG combine to detect opportunities to replace (i64 (any_extend... · d4f4a1ba
  Craig Topper authored Jun 25, 2021
  d4f4a1ba
- [ms] [llvm-ml] Disable C-style comments · e074d580
  Eric Astor authored Jun 25, 2021
  
  e074d580
- [X86] Selecting fld0 for undefined value in fast ISEL. · 36003c20
  Luo, Yuanke authored Jun 22, 2021
  36003c20
- Disable ReplaceLDS pass, patch up tests to match · 50ad3478
  Jon Chesterfield authored Jun 26, 2021
  50ad3478
Jun 25, 2021
- [PowerPC] Disable combine 64-bit bswap(load) without LDBRX · 4e22c726
  Nemanja Ivanovic authored Jun 25, 2021
  4e22c726
- [SystemZ] Add support for .reloc assembler directive · b2674670
  Ulrich Weigand authored Jun 25, 2021
  b2674670
- [X86] Simplify part of the isel for X86ISD::FCMP/STRICT_FCMP/STRICT_FCMPS. · 0f3bc00a
  Craig Topper authored Jun 25, 2021
  0f3bc00a