Commits · fcd0cb39214e5abc89bfb1926397fe668172ecaa · Roger Ferrer / llvm-epi · GitLab

Jun 30, 2021
- [MTE] Remove redundant helper function. · a24f1046
  Florian Mayer authored Jun 29, 2021
  a24f1046
- Recommit "[AArch64] Custom lower <4 x i8> loads" · b062fff8
  Sjoerd Meijer authored Jun 29, 2021
  b062fff8
Jun 29, 2021
- CodeGen: Store LLT instead of uint64_t in MachineMemOperand · 990278d0
  Matt Arsenault authored May 19, 2021
  990278d0
- [SVE] Added CodeGen support for inserting an element into a predicate vector · c3d3defd
  Dylan Fleming authored Jun 29, 2021
  c3d3defd
Jun 28, 2021
- Revert "[AArch64] Custom lower <4 x i8> loads" · 3a7cea28
  Sjoerd Meijer authored Jun 28, 2021
  3a7cea28
- [AArch64][SVE] DAG combine SETCC_MERGE_ZERO of a SETCC_MERGE_ZERO · c089e29a
  Bradley Smith authored Jun 25, 2021
  c089e29a
- [AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX · f9f5d415
  Brendon Cahoon authored Apr 30, 2021
  f9f5d415
- [Aarch64] Adding support for Armv9-A Realm Management Extension · 88b1135e
  Lucas Prates authored Jun 22, 2021
  88b1135e
Jun 26, 2021
- [ISel] Port AArch64 SABD and UABD to DAGCombine · 2887f146
  David Green authored Jun 26, 2021
  2887f146
Jun 25, 2021
- Revert "[GlobalISel] NFC: Have LLT::getSizeInBits/Bytes return a TypeSize." · b732e6c9
  Sander de Smalen authored Jun 25, 2021
  b732e6c9
- [GlobalISel] NFC: Have LLT::getSizeInBits/Bytes return a TypeSize. · aeab9d95
  Sander de Smalen authored Jun 25, 2021
  aeab9d95
- [GlobalISel] NFC: Change LLT::changeNumElements to LLT::changeElementCount. · c9acd2f3
  Sander de Smalen authored Jun 25, 2021
  c9acd2f3
- [AArch64] Custom lower <4 x i8> loads · 51e434fc
  Sjoerd Meijer authored Jun 24, 2021
  51e434fc
Jun 24, 2021
- [llvm] Rename StringRef _lower() method calls to _insensitive() · 42f74e82
  Martin Storsjö authored Jun 23, 2021
  42f74e82
- [AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP) · 571c8c52
  Pablo Barrio authored Jun 15, 2021
  571c8c52
- [CostModel][AArch64] Improve cost model for vector reduction intrinsics · 0c4651f0
  Rosie Sumpter authored Jun 15, 2021
  0c4651f0
- [GlobalISel] NFC: Change LLT::vector to take ElementCount. · d5e14ba8
  Sander de Smalen authored Jun 24, 2021
  d5e14ba8
Jun 23, 2021
- Revert "[AArch64LoadStoreOptimizer] Recommit: Generate more STPs by renaming registers earlier" · 1cb7849a
  Martin Storsjö authored Jun 23, 2021
  1cb7849a
Jun 22, 2021
- [AArch64LoadStoreOptimizer] Recommit: Generate more STPs by renaming registers earlier · ea011ec5
  Meera Nakrani authored Jun 14, 2021
  ea011ec5
- Rename MachineMemOperand::getOrdering -> getSuccessOrdering. · 74909e4b
  Eli Friedman authored Jun 21, 2021
  74909e4b
Jun 21, 2021
- [AArch64][X86] Allow 64-bit label differences lower to IMAGE_REL_*_REL32 · c6186922
  Fangrui Song authored Jun 21, 2021
  c6186922
- [AArch64][SVE] Wire up vscale_range attribute to SVE min/max vector queries · 9e7329e3
  Bradley Smith authored Jun 04, 2021
  9e7329e3
Jun 20, 2021
- Fix -Wunused-variable and -Wunused-but-set-variable in -DLLVM_ENABLE_ASSERTIONS=off build. NFC · 521d3732
  Fangrui Song authored Jun 20, 2021
  
  521d3732
Jun 18, 2021
- [AArch64] Add TableGen patterns to generate uaddlv · 78b75b45
  Jingu Kang authored Jun 14, 2021
  78b75b45
Jun 17, 2021
- [AArch64][GISel] and+or+shl => bfi · 7b061208
  Jon Roelofs authored May 27, 2021
  7b061208
Jun 16, 2021
- [SVE] Selection failure with scalable insertelements · 2a936be3
  Dylan Fleming authored Jun 16, 2021
  2a936be3
- [llvm][AArch64] Handle arrays of struct properly (from IR) · e4ecd83f
  David Spickett authored Jun 09, 2021
  e4ecd83f
Jun 15, 2021
- [SVE][LSR] Teach LSR to enable simple scaled-index addressing mode generation for SVE. · 1c096bf0
  Huihui Zhang authored Jun 14, 2021
  1c096bf0
Jun 14, 2021
- [AArch64] Improve SAD pattern · 08ce52ef
  Jingu Kang authored Jun 10, 2021
  08ce52ef
Jun 11, 2021
- [CostModel][AArch64] Improve the cost estimate of CTPOP intrinsic · d7c219a5
  Rosie Sumpter authored Jun 09, 2021
  d7c219a5
- [Analysis] Pass RecurrenceDescriptor as const reference. NFCI. · 5e6bfb66
  Simon Pilgrim authored Jun 11, 2021
  5e6bfb66
- [AArch64][GlobalISel] Fix incorrectly generating uxtw/sxtw for addressing modes. · 670edf3e
  Amara Emerson authored Jun 10, 2021
  670edf3e
- [AArch64][GlobalISel] Legalize scalar G_CTTZ + G_CTTZ_ZERO_UNDEF · 933df6ca
  Jessica Paquette authored Jun 10, 2021
  933df6ca
Jun 10, 2021
- [AArch64][GlobalISel] Mark some G_BITREVERSE types as legal + select them · 1b894ccd
  Jessica Paquette authored Jun 09, 2021
  1b894ccd
- [AArch64] Silence fallthrough warning. NFC. · 3dceffd0
  Benjamin Kramer authored Jun 10, 2021
  3dceffd0
- [AArch64] Add cost tests for bitreverse · de79919e
  Irina Dobrescu authored Jun 03, 2021
  de79919e
- Revert "[AArch64LoadStoreOptimizer] Generate more STPs by renaming registers earlier" · 99653702
  Martin Storsjö authored Jun 10, 2021
  99653702
Jun 09, 2021
- [AArch64LoadStoreOptimizer] Generate more STPs by renaming registers earlier · d96ea466
  Meera Nakrani authored Jun 02, 2021
  d96ea466
Jun 08, 2021
- [CostModel] Return an invalid cost for memory ops with unsupported types · 5db52751
  Kerry McLaughlin authored Jun 08, 2021
  5db52751
Jun 07, 2021
- [AArch64][SVE] Improve codegen for dupq SVE ACLE intrinsics · 60c9b5f3
  Bradley Smith authored May 20, 2021
  60c9b5f3