Commits · fceadbcb335da23d0a9beba8c4080a3e4222a385 · Roger Ferrer / llvm-epi · GitLab

Jun 24, 2020
- [AArch64][GlobalISel] Improve codegen for some constant vectors by using constant pool loads. · fceadbcb
  Amara Emerson authored Jun 22, 2020
  fceadbcb
- Remove GlobalValue::getAlignment(). · a2caa3b6
  Eli Friedman authored May 18, 2020
  a2caa3b6
- [SimplifyCFG] Drop debug loc in SpeculativelyExecuteBB · f8bd6a75
  Vedant Kumar authored Jun 23, 2020
  f8bd6a75
- AMDGPU/GlobalISel: Fix fixed ABI special VGPR function arguments · a162048a
  Matt Arsenault authored Jun 23, 2020
  a162048a
- [NFC] Remove outdated comment in llvm-symbolizer test case. · c2bb88cc
  Amy Huang authored Jun 23, 2020
  
  c2bb88cc
- [AArch64][SVE] Add legalization support for i32/i64 vector srem/urem · e9d4e34a
  Eli Friedman authored Jun 08, 2020
  e9d4e34a
- [IR] Prefer scalar type for struct indexes in GEP constant expressions. · 90ad7869
  Eli Friedman authored Jun 17, 2020
  90ad7869
Jun 23, 2020
- [RISCV][NFC] Add tests for folds of ADDIs into load/stores · 0947a8ca
  Luís Marques authored Jun 23, 2020
  0947a8ca
- [ARM] Mark more integer instructions as not having side effects. · d604cc6e
  David Green authored Jun 23, 2020
  d604cc6e
- [ARM] Cortex-M4 integer instructions scheduler info test. NFC · 887c0b56
  David Green authored Jun 23, 2020
  887c0b56
- [ASan][MSan] Remove EmptyAsm and set the CallInst to nomerge to avoid from merging. · 6a822e20
  Zequan Wu authored Jun 22, 2020
  6a822e20
- [DSE,MSSA] Treat `store 0` after calloc as noop stores. · ff4de868
  Florian Hahn authored Jun 23, 2020
  ff4de868
- [AMDGPU/MemOpsCluster] Implement new heuristic for computing max mem ops cluster size · cc9d6938
  Your Name authored Jun 24, 2020
  cc9d6938
- Fix incorrect "REQUIRE" (default_target->default_triple) introduced in 59f45a1c · 8b64adb0
  Mehdi Amini authored Jun 23, 2020
  8b64adb0
- [X86][AVX] Attempt to lower v16i32/v16f32 shuffles with lowerShuffleAsRepeatedMaskAndLanePermute · e7e204a3
  Simon Pilgrim authored Jun 23, 2020
  e7e204a3
- [X86][AVX] Add v16f32 variant of PR46249 test case · f9b4b8e3
  Simon Pilgrim authored Jun 23, 2020
  
  f9b4b8e3
- [NewPM] Attempt to run opt passes specified via -foo-pass under NPM · 23f5fd85
  Arthur Eubanks authored Jun 19, 2020
  23f5fd85
- [X86][AVX] Add PR46249 test case · f3c61b56
  Simon Pilgrim authored Jun 23, 2020
  
  f3c61b56
- [PhaseOrdering] add test for missed vectorization; NFC (PR43745) · a809cea6
  Sanjay Patel authored Jun 23, 2020
  a809cea6
- [ObjectYAML][ELF] Add support for emitting the .debug_pubtypes section. · fad54c50
  Xing GUO authored Jun 23, 2020
  fad54c50
- [ARM] Describe defs/uses of VLLDM and VLSTM · adf7973f
  Momchil Velikov authored Jun 23, 2020
  adf7973f
- [openmp] Base of tablegen generated OpenMP common declaration · d90443b1
  Valentin Clement authored Jun 23, 2020
  d90443b1
- [BFloat] Add convert/copy instrinsic support · 3f353a2e
  Mikhail Maltsev authored Jun 23, 2020
  3f353a2e
- AMDGPU/GlobalISel: Fix asserts on non-s32 sitofp/uitofp sources · db777eae
  Matt Arsenault authored Jun 12, 2020
  db777eae
- [PhaseOrdering] add test for vectorizer cooperation; NFC · df794431
  Sanjay Patel authored Jun 23, 2020
  df794431
- [ObjectYAML][ELF] Add support for emitting the .debug_pubnames section. · 8c7775e9
  Xing GUO authored Jun 23, 2020
  8c7775e9
- [ARM] BFloat MatMul Intrinsics&CodeGen · 9c579540
  Mikhail Maltsev authored Jun 23, 2020
  9c579540
- [AMDGPU/MemOpsCluster] Compute `width` for `MIMG` instruction class. · 5832950a
  hsmahesha authored Jun 23, 2020
  5832950a
- [AArch64][SVE] ACLE: Add bfloat16 to struct load/stores. · 121e585e
  Sander de Smalen authored Jun 23, 2020
  121e585e
- [SVE][CodeGen] Legalisation of vsetcc with scalable types · 50805031
  Kerry McLaughlin authored Jun 23, 2020
  50805031
- [IndVarSimplify] Don't replace IV user with unsafe loop-invariant (PR45360) · d57e9aca
  Roman Lebedev authored Jun 23, 2020
  d57e9aca
- [PowerPC] fold addi's imm operand to its imm form consumer's displacement · 7ab05d9a
  Chen Zheng authored Jun 18, 2020
  7ab05d9a
- [SVE] Code generation for fixed length vector loads & stores. · 499c6328
  Paul Walker authored May 18, 2020
  499c6328
- [AVR] Rewrite the function calling convention. · b9c26a9c
  Dylan McKay authored Jun 19, 2020
  b9c26a9c
- [PowerPC][NFC] Add tests for variadic functions on PPC64 · f09ef03e
  Kai Luo authored Jun 23, 2020
  
  f09ef03e
- [DebugInfo] Print line table extended opcode bytes if parsing fails · 9782c922
  James Henderson authored Jun 17, 2020
  9782c922
- [llvm-rc] Implement the language id option · f36f8b41
  Martin Storsjö authored Jun 20, 2020
  f36f8b41
- [SROA] Teach SROA to perform no-op pointer conversion. · f95850ce
  Michael Liao authored Jun 16, 2020
  f95850ce
- [InstCombine] Replace selects with Phis · 9bff376e
  Max Kazantsev authored Jun 23, 2020
  9bff376e
- [SDAG] Add new AssertAlign ISD node. · b1360caa
  Michael Liao authored May 24, 2020
  b1360caa