Commits · fdc902774e7ae0dae0833216500da047c7c4bec6 · Roger Ferrer / llvm-epi · GitLab

Jul 29, 2020
- [DAG][AMDGPU][X86] Add SimplifyMultipleUseDemandedBits handling for... · fdc90277
  Simon Pilgrim authored Jul 29, 2020
  fdc90277
- [Statepoint] When using the tied def lowering, unconditionally use vregs [almost NFC] · 31342eb6
  Philip Reames authored Jul 29, 2020
  31342eb6
- [X86][SSE] getV4X86ShuffleImm8 - canonicalize broadcast masks · 0c005be6
  Simon Pilgrim authored Jul 29, 2020
  0c005be6
- [X86] Add FeatureCMPXCHG8B and FeatureSlowUAMem16 to 'lakemont' in X86.td · 06cf6f77
  Craig Topper authored Jul 28, 2020
  06cf6f77
Jul 28, 2020
- [X86] Remove disabled miscompiling X86CondBrFolding pass · e1dd212c
  Roman Lebedev authored Jul 28, 2020
  e1dd212c
- [DAG] isSplatValue - add support for TRUNCATE/SIGN_EXTEND/ZERO_EXTEND · b4b6e774
  Simon Pilgrim authored Jul 28, 2020
  b4b6e774
- [X86][XOP] Shuffle v16i8 using VPPERM(X,Y) instead of OR(PSHUFB(X),PSHUFB(Y)) · 4838cd46
  Simon Pilgrim authored Jul 28, 2020
  
  4838cd46
- [X86][SSE] Attempt to match OP(SHUFFLE(X,Y),SHUFFLE(X,Y)) -> SHUFFLE(HOP(X,Y)) · 18211177
  Simon Pilgrim authored Jul 28, 2020
  18211177
- [X86] Detect if EFLAGs is live across XBEGIN pseudo instruction. Add it as... · 647e861e
  Craig Topper authored Jul 27, 2020
  647e861e
Jul 27, 2020
- [X86][SSE] Relax 128-bit restriction on... · 4d84d949
  Simon Pilgrim authored Jul 27, 2020
  4d84d949
- [X86][AVX] Fold extract_subvector(truncate(x),0) -> truncate(extract_subvector(x),0) · ab4ffa52
  Simon Pilgrim authored Jul 27, 2020
  ab4ffa52
Jul 26, 2020
- [X86] Turn X86DAGToDAGISel::tryVPTERNLOG into a fully custom instruction... · df12524e
  Craig Topper authored Jul 26, 2020
  df12524e
- [X86][SSE] lowerV2I64Shuffle - use undef elements in PSHUFD mask widening · 17eafe08
  Simon Pilgrim authored Jul 26, 2020
  17eafe08
- [X86] Add masked versions of the VPTERNLOG test cases added for D83630. NFC · c5b23714
  Craig Topper authored Jul 25, 2020
  c5b23714
Jul 25, 2020
- [Statepoints] Support lowering gc relocations to virtual registers · 3da1a963
  Philip Reames authored Jul 11, 2020
  3da1a963
- [X86] Add llvm.roundeven test cases. Add f80 tests cases for constrained... · 9182dc78
  Craig Topper authored Jul 25, 2020
  9182dc78
- [X86] Fix intrinsic names in strict fp80 tests to use f80 in their names instead of x86_fp80. · 60a5799e
  Craig Topper authored Jul 25, 2020
  60a5799e
- [X86] Remove stress-scheduledagrrlist.ll. · c09a1084
  Florian Hahn authored Jul 25, 2020
  c09a1084
- [X86][SSE] getFauxShuffle - ignore undemanded sources for PACKSS/PACKUS faux shuffles · 66998ae5
  Simon Pilgrim authored Jul 25, 2020
  66998ae5
Jul 24, 2020
- [LegalizeTypes] Teach DAGTypeLegalizer::GenWidenVectorLoads to pad with undef... · 8131e190
  Craig Topper authored Jul 23, 2020
  8131e190
Jul 23, 2020
- [IR] Add min/max/abs intrinsics · deb4bb2b
  Nikita Popov authored Jul 19, 2020
  deb4bb2b
- [X86][SSE] Add additional (f)add(shuffle(x,y),shuffle(x,y)) tests for D83789 · bfc4294e
  Simon Pilgrim authored Jul 23, 2020
  
  bfc4294e
- [X86][SSE] SimplifyDemandedVectorEltsForTargetNode - add SSE shift multiple use handling · d720ba1e
  Simon Pilgrim authored Jul 23, 2020
  d720ba1e
- [ScheduleDAGRRList] Limit number of candidates to explore. · 2f8e6b5f
  Florian Hahn authored Jul 23, 2020
  2f8e6b5f
- [X86] Rework the "sahf" feature flag to only apply to 64-bit mode. · b2c65beb
  Craig Topper authored Jul 22, 2020
  b2c65beb
Jul 21, 2020
- [X86][AVX] getTargetShuffleMask - don't decode VBROADCAST(EXTRACT_SUBVECTOR(X,0)) patterns. · 5b5dc244
  Simon Pilgrim authored Jul 21, 2020
  5b5dc244
- [MBP] Use profile count to compute tail dup cost if it is available · 28759e9f
  Guozhi Wei authored Jul 21, 2020
  28759e9f
Jul 20, 2020
- [llc] (almost) remove `--print-machineinstrs` · 589c646a
  Yuanfang Chen authored Jul 20, 2020
  589c646a
- IR: Define byref parameter attribute · 5e999cbe
  Matt Arsenault authored Jun 05, 2020
  5e999cbe
- [llvm-readobj] Update tests because of changes in llvm-readobj behavior · b36a3e61
  Elvina Yakubova authored Jul 20, 2020
  b36a3e61
- [NFC][SimplifyCFG] Add standalone test for common code hoisting xform option · 3de41663
  Roman Lebedev authored Jul 20, 2020
  3de41663
Jul 19, 2020
- [x86] split FMA with fast-math-flags to avoid libcall · 50afa187
  Sanjay Patel authored Jul 19, 2020
  50afa187
Jul 17, 2020
- [x86] add tests for FMA with FMF; NFC · 7598ad3e
  Sanjay Patel authored Jul 16, 2020
  
  7598ad3e
- [MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics · 62fd7f76
  Jay Foad authored Jan 07, 2020
  62fd7f76
- [X86] Change the scheduler model for 'pentium4' to SandyBridgeModel. · 6bba9583
  Craig Topper authored Jul 16, 2020
  6bba9583
Jul 16, 2020
- [X86] Move integer hadd/hsub formation into a helper function shared by combineAdd and combineSub. · 5408024f
  Craig Topper authored Jul 16, 2020
  5408024f
- [X86] Change the tuning settings for pentium4 to be more modern since its the... · ad171d24
  Craig Topper authored Jul 16, 2020
  ad171d24
- [X86] Add test case for PR46455. · 9adf7461
  Craig Topper authored Jul 16, 2020
  
  9adf7461
- MIR Statepoint refactoring. Part 1: Basic MI level changes. · ef658ebd
  Denis Antrushin authored Jun 10, 2020
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- Remove TwoAddressInstructionPass::sink3AddrInstruction. · 60433c63
  James Y Knight authored Jul 16, 2020
  60433c63