Commits · fe42ebe442bdf4842cdc66b2c69a8dfa78f5c75b · Roger Ferrer / llvm-epi · GitLab

Dec 07, 2022
- [AMDGPU][GlobalISel] Fix legalizing image intrinsics for new types · fe42ebe4
  Mirko Brkusanin authored Dec 07, 2022
  fe42ebe4
- [llvm-exegesis] Dry run mode · 7a761402
  Roman Lebedev authored Dec 07, 2022
  7a761402
- [NFC] Port all (but one) LoopUnroll tests to `-passes=` syntax · 5103ef64
  Roman Lebedev authored Dec 07, 2022
  
  5103ef64
- [AMDGPU] Add gfx11 runline to omod test. NFC · c6c4f54e
  Joe Nash authored Dec 07, 2022
  
  c6c4f54e
- [X86] Pre-commit test for pr59305 · fc16ca71
  Phoebe Wang authored Dec 08, 2022
  
  fc16ca71
- [RISCV][JitLink] Propagate error from Expected<T> result during R_RISCV_PCREL_HI20 parsing · a2c9f12d
  Dmitry Kurtaev authored Dec 07, 2022
  a2c9f12d
- Automate tests. · f7d426b3
  Doru Bercea authored Dec 06, 2022
  
  f7d426b3
- [InstCombine] fold more icmp + select patterns by distributive laws · b4c8cfc7
  chenglin.bi authored Dec 07, 2022
  b4c8cfc7
- [Instcombine] Canonicalize ~((A & B) ^ (A | ?)) -> (A & B) | ~(A | ?) · 10c3df72
  chenglin.bi authored Dec 07, 2022
  10c3df72
- [SCEV] Use umin_seq for symbolic max BE count · 4d97a914
  Nikita Popov authored Dec 07, 2022
  4d97a914
- [SCEV] Add another symbolic BE count test (NFC) · dcfe2e7a
  Nikita Popov authored Dec 07, 2022
  
  dcfe2e7a
- [X86] combine-and.ll - add some 256/512-bit test coverage for D138521 · 519adee2
  Simon Pilgrim authored Dec 07, 2022
  
  519adee2
- [X86] combine-and.ll - add AVX1 test coverage · abe6dbee
  Simon Pilgrim authored Dec 07, 2022
  
  abe6dbee
- [llvm] Auto-cleanup left-over file from earlier version of this test on bots · bfe292b0
  Nico Weber authored Dec 07, 2022
  bfe292b0
- [Test] Add a test where we expect to see symbolic max as umin_seq · af7a8866
  Max Kazantsev authored Dec 07, 2022
  
  af7a8866
- Fix a typo ll->llc in test · 3abdd9b9
  Haojian Wu authored Dec 07, 2022
  
  3abdd9b9
- Add implementation isTargetCanonicalConstantNode for hexagon. · a2215149
  Haojian Wu authored Dec 07, 2022
  a2215149
- [AMDGPU] G_IS_FPCLASS lower() support for IEEE fp types · 587747d8
  Janek van Oirschot authored Dec 06, 2022
  587747d8
- [SCEV] Remember blocks for which we know symbolic exit count but not exact · 07de5d18
  Max Kazantsev authored Dec 07, 2022
  07de5d18
- [MachineCombiner] Extend reassociation logic to handle inverse instructions · f8ed7093
  Anton Sidorenko authored Oct 14, 2022
  f8ed7093
- [AMDGPU] Fix wide spills · 1e3abd82
  Piotr Sobczak authored Dec 02, 2022
  1e3abd82
- [SVE] Change some bfloat lane intrinsics to use i32 immediates · bfb6f47e
  David Sherwood authored Nov 28, 2022
  bfb6f47e
- [InstCombine] Add tests for (X << Z) / (X * Y) -> (1 << Z) / Y. nfc · 463e9be1
  Chenbing Zheng authored Dec 07, 2022
  
  463e9be1
- [LICM] Remove custom isInstInList() implementation (PR59324) · ed760741
  Nikita Popov authored Dec 07, 2022
  ed760741
- [PowerPC] Support test data class intrinsic of 128-bit float · 62f20f51
  Qiu Chaofan authored Dec 07, 2022
  62f20f51
- [VP][RISCV] Recommit "Add vp.fshl/fshr and RISC-V support." · 0f8c761c
  Yeting Kuo authored Dec 07, 2022
  0f8c761c
- [AMDGPU] Handle `min(max(x, y), max(min(x, y), z))` in med3 combines · bcfdaa96
  Justin Bogner authored Dec 06, 2022
  bcfdaa96
- [AMDGPU] Handle nnan and fast on the call in fpmed3 patterns · 916ae0a0
  Justin Bogner authored Dec 06, 2022
  916ae0a0
- [AMDGPU] Precommit GISel test for min(max(x, y), max(min(x, y), z)) -> med3 · f1353d2f
  Justin Bogner authored Dec 06, 2022
  f1353d2f
- [Propeller] Use Fixed MBB ID instead of volatile MachineBasicBlock::Number. · 6015a045
  Rahman Lavaee authored Dec 06, 2022
  6015a045
- Revert "[VP][RISCV] Add vp.fshl/fshr and RISC-V support." · 7883e5b0
  Kazu Hirata authored Dec 06, 2022
  7883e5b0
- [AMDGPU] Precommit GISel test showing missing med3 combines · 6ec24c1d
  Justin Bogner authored Dec 06, 2022
  6ec24c1d
- [RISCV] Add basic cost model for vp float rounding instructions. · 8c8a6e14
  Yeting Kuo authored Dec 06, 2022
  8c8a6e14
- [RISCV] Codegen support for Zfhmin. · 7b50c183
  Monk Chiang authored Nov 30, 2022
  7b50c183
- [llvm-profdata] Drop profile symbol list during merging AutoFDO profiles. · ad03f407
  Hongtao Yu authored Dec 06, 2022
  ad03f407
- [VP][RISCV] Add vp.fshl/fshr and RISC-V support. · 70de0e01
  Yeting Kuo authored Nov 20, 2022
  70de0e01
- [RISCV][CostModel] Add a test for reverse shuffles cost on RISCV, NFC · cfd73186
  liqinweng authored Dec 07, 2022
  cfd73186
- [NFC][SimplifyCFG] Add more fold-branch-to-common-dest tests · ea7ad8b3
  Roman Lebedev authored Dec 07, 2022
  
  ea7ad8b3
- [ConstraintElim] Fix sort order to not comparing insts in different bbs. · 9eda7810
  Florian Hahn authored Dec 06, 2022
  9eda7810
- [RISCV] Move VSPILL/VRELOAD expansion for vector tuples to eliminateFrameIndex. · 8d30b9e6
  Craig Topper authored Dec 06, 2022
  8d30b9e6