Commits · fe558efe71c12a665d4e1b5e7638baaacfe84cf7 · Roger Ferrer / llvm-epi · GitLab

May 02, 2023
- [RISCV][CodeGen] Support Zfinx codegen · fe558efe
  Shao-Ce SUN authored May 01, 2023
  fe558efe
- [ARM] Don't allocate memory if free space in segmented stack is just enough · 1d0ccebc
  Zhiyao Ma authored May 02, 2023
  1d0ccebc
- [AArch64] Add sign bits handling for vector compare nodes · 41549b53
  David Green authored May 02, 2023
  41549b53
- [SelectionDAG] Use int64_t to store the integer power of llvm.powi · 8f966ced
  Shengchen Kan authored May 02, 2023
  8f966ced
- [RISCV] Add Smaia and Ssaia extensions support · 74c1fa60
  4vtomat authored Apr 11, 2023
  74c1fa60
- Revert "[SelectionDAG] Use logic right shift to avoid loop hang" · 4e4db6f6
  Shengchen Kan authored May 02, 2023
  4e4db6f6
- [SelectionDAG] Use logic right shift to avoid loop hang · b73229e5
  Shengchen Kan authored May 02, 2023
  b73229e5
- [RISCV] Use vslide1down idiom for generic build_vector · 35d218e9
  Philip Reames authored May 01, 2023
  35d218e9
- [RISCV][InsertVSETVLI] Avoid VL toggles for extractelement patterns · 657d20dc
  Philip Reames authored May 01, 2023
  657d20dc
May 01, 2023
- [RISCV] Move NTLH hint emission into RISCVAsmPrinter.cpp. · 13fe6733
  Craig Topper authored May 01, 2023
  13fe6733
Apr 30, 2023
- [RISCV] Prevent lowerVectorStrictFSetcc from creatin an ISD::AND with identical operands. · e56c6f3a
  Craig Topper authored Apr 29, 2023
  e56c6f3a
- [M68k] Add instruction selection support for zext with PCD addressing · 34b37c00
  Ian Douglas Scott authored Apr 29, 2023
  34b37c00
Apr 29, 2023
- [ARM] Add predicated shift patterns · f1961153
  David Green authored Apr 29, 2023
  f1961153
- [TargetLowering] Don't use ISD::SELECT_CC in expandFP_TO_INT_SAT. · df017ba9
  Craig Topper authored Apr 29, 2023
  df017ba9
- [AMDGPU] Place global constructors in .init_array and .fini_array · a1da7461
  Joseph Huber authored Apr 27, 2023
  a1da7461
- LangRef: Add "dynamic" option to "denormal-fp-math" · bc37be18
  Matt Arsenault authored Dec 06, 2022
  bc37be18
- [X86] Fix the vnni machine combine issue. · 40222ddc
  Luo, Yuanke authored Apr 29, 2023
  40222ddc
- [RISCV] Add a DAG combine to fold (add (xor (setcc X, Y), 1) -1)->(neg (setcc X, Y)). · 57841375
  Craig Topper authored Apr 28, 2023
  
  57841375
Apr 28, 2023
- [RISCV] Introduce unaligned-vector-mem feature · d636bcb6
  Philip Reames authored Apr 28, 2023
  d636bcb6
- [ARM] Enable shouldFoldSelectWithIdentityConstant for MVE · d321f3aa
  David Green authored Apr 28, 2023
  d321f3aa
- [EarlyCSE] Do not CSE convergent calls in different basic blocks · 56af0e91
  Jay Foad authored Apr 27, 2023
  56af0e91
- [CSE] Precommit an AMDGPU test case for D149348 · 5534d1d8
  Jay Foad authored Apr 27, 2023
  5534d1d8
- [AArch64] Add preserve_all calling convention. · d75e70d7
  Daniel Kiss authored Apr 28, 2023
  d75e70d7
- [ARM] Update and regenerate pred-selectop test. NFC · 5ff493df
  David Green authored Apr 28, 2023
  5ff493df
- [LICM] Don't duplicate instructions just because they're free · 0659000f
  Nikita Popov authored Apr 26, 2023
  0659000f
- [RISCV] Fix labels in fixed-vectors-fp test · 32dbe0f5
  Luke Lau authored Apr 28, 2023
  
  32dbe0f5
- [AArch64] Add support for efficient bitcast in vector truncate store. · cd68e17b
  Lawrence Benson authored Apr 28, 2023
  cd68e17b
- [AArch64][FastISel] Handle CRC32 intrinsics · ab21beac
  Alexis Engelke authored Apr 21, 2023
  ab21beac
- [RISCV] Add tests for illegal fixed length vectors that need widened · bd6fa865
  Luke Lau authored Apr 14, 2023
  bd6fa865
- [hwasan] fix false positive when hwasan-match-all-tag flag is enabled and short granules are used · d961f66b
  Enna1 authored Apr 28, 2023
  d961f66b
- [hwasan][test] add test for hwasan-check-memaccess when hwasan-match-all-tag... · 9baa8527
  Enna1 authored Apr 28, 2023
  9baa8527
- Revert "[CodeGenPrepare] Estimate liveness of loop invariants when checking... · fbf42f1f
  Jordan Rupprecht authored Apr 27, 2023
  fbf42f1f
- [AMDGPU] Track liveins for max-ilp-sched-strategy · 7f0a881e
  Jeffrey Byrnes authored Apr 27, 2023
  7f0a881e
Apr 27, 2023
- [CodeGen][MachineLastInstrsCleanup] fix INLINEASM_BR hazard · 012ea747
  Nick Desaulniers authored Apr 27, 2023
  012ea747
- [CodeGen] precommit machine-latecleanup test · 095a0c67
  Nick Desaulniers authored Apr 27, 2023
  095a0c67
- AMDGPU: Define sub-class of SGPR_64 for tail call return · 1ab8b9ae
  Changpeng Fang authored Apr 27, 2023
  1ab8b9ae
- [AArch64] Regenerate trunc-to-tbl and zext-to-tbl tests. NFC · 4249d609
  David Green authored Apr 27, 2023
  4249d609
- [AMDGPU] Legalize soffset of buffer instructions. Use Waterfall loop logic. · e016fb57
  skc7 authored Jan 03, 2023
  e016fb57
- [AArch64] Precommit tests for VECTOR_SHUFFLE · 044f27f6
  Jingu Kang authored Apr 27, 2023
  
  044f27f6
- [IR] Change shufflevector undef mask to poison · 8b56da5e
  ManuelJBrito authored Apr 26, 2023
  8b56da5e