Commits · 275a4f76c4b9f15cc0f73c38b8f9ee12e0e477d5 · Raul Torres / llvm-target-spread · GitLab

Sep 29, 2017
- AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC · ce4ddd06
  Nicolai Haehnle authored Sep 29, 2017
  ce4ddd06
Aug 01, 2017
- AMDGPU: Initial implementation of calls · b62a4eb5
  Matt Arsenault authored Aug 01, 2017
  b62a4eb5
Jul 24, 2017
- AMDGPU: Fix allocating pseudo-registers · 7052a6a5
  Matt Arsenault authored Jul 24, 2017
  7052a6a5
Jul 21, 2017
- AMDGPU: Add instruction definitions for some scratch_* instructions · ca7b0a17
  Matt Arsenault authored Jul 21, 2017
  ca7b0a17
Jul 18, 2017
- AMDGPU: Figure out private memory regs after lowering · 1cc47f84
  Matt Arsenault authored Jul 18, 2017
  1cc47f84
- [AMDGPU][MC] Corrected disassembler for proper decoding of v_mqsad_u32_u8 · 30fc5239
  Dmitry Preobrazhensky authored Jul 18, 2017
  30fc5239
Mar 21, 2017
- AMDGPU: Fix not including v2i16/v2f16 in register class · 5af82a7a
  Matt Arsenault authored Mar 21, 2017
  5af82a7a
Feb 27, 2017
- AMDGPU: Add VOP3P instruction format · 9be7b0d4
  Matt Arsenault authored Feb 27, 2017
  9be7b0d4
Feb 21, 2017
- AMDGPU: Don't use stack space for SGPR->VGPR spills · e0bf7d02
  Matt Arsenault authored Feb 21, 2017
  e0bf7d02
Feb 18, 2017
- AMDGPU: Merge initial gfx9 support · e823d92f
  Matt Arsenault authored Feb 18, 2017
  e823d92f
Dec 14, 2016
- AMDGPU: Make AllocationPriority of SGPRs higher than VGPRs · bdc0ac0a
  Matt Arsenault authored Dec 14, 2016
  bdc0ac0a
Dec 10, 2016
- AMDGPU: Fix handling of 16-bit immediates · 4bd72361
  Matt Arsenault authored Dec 10, 2016
  4bd72361
Dec 09, 2016
- AMDGPU: Allow TBA, TMA, TTMP* registers with SMEM instructions · 52facf01
  Matt Arsenault authored Dec 09, 2016
  52facf01
Dec 05, 2016
- AMDGPU: Assembler support for exp · bf6bdac1
  Matt Arsenault authored Dec 05, 2016
  bf6bdac1
- AMDGPU: Change how exp is printed · 8a63cb90
  Matt Arsenault authored Dec 05, 2016
  8a63cb90
Nov 29, 2016
- AMDGPU: Disallow exec as SMEM instruction operand · 640c44b8
  Matt Arsenault authored Nov 29, 2016
  640c44b8
Nov 25, 2016
- AMDGPU/SI: Add back reverted SGPR spilling code, but disable it · 79c05871
  Marek Olsak authored Nov 25, 2016
  79c05871
- Revert "AMDGPU: Make m0 unallocatable" · a45dae45
  Marek Olsak authored Nov 25, 2016
  a45dae45
Nov 24, 2016
- AMDGPU: Make m0 unallocatable · 9e5c7b10
  Matt Arsenault authored Nov 24, 2016
  9e5c7b10
Nov 13, 2016
- [AMDGPU] Add f16 support (VI+) · f86e4b72
  Konstantin Zhuravlyov authored Nov 13, 2016
  f86e4b72
Nov 10, 2016
- AMDGPU: Add VI i16 support · 115a6156
  Tom Stellard authored Nov 10, 2016
  115a6156
Nov 04, 2016
- Revert "AMDGPU: Add VI i16 support" · 2d2d33f1
  Tom Stellard authored Nov 04, 2016
  2d2d33f1
Nov 03, 2016
- AMDGPU: Add VI i16 support · 2b3379cd
  Tom Stellard authored Nov 03, 2016
  2b3379cd
Nov 01, 2016
- AMDGPU: Whitespace fixes · f3dd8630
  Matt Arsenault authored Nov 01, 2016
  f3dd8630
Sep 09, 2016
- AMDGPU : Fix mqsad_u32_u8 instruction incorrect data type. · 06f8d394
  Wei Ding authored Sep 09, 2016
  06f8d394
- AMDGPU] Assembler: better support for immediate literals in assembler. · 1eeb11bf
  Sam Kolton authored Sep 09, 2016
  1eeb11bf
Sep 07, 2016
- Remove unnecessary call to getAllocatableRegClass · 6cda10c9
  Matt Arsenault authored Sep 07, 2016
  6cda10c9
Sep 03, 2016
- AMDGPU: Set sizes of spill pseudos · ac42ba86
  Matt Arsenault authored Sep 03, 2016
  ac42ba86
Jul 21, 2016
- [AMDGPU] Some code cleaning in SIRegisterInfo.td · 6c4efcad
  Sam Kolton authored Jul 21, 2016
  6c4efcad
Jul 19, 2016
- AMDGPU: Expand register indexing pseudos in custom inserter · cb540bc0
  Matt Arsenault authored Jul 19, 2016
  cb540bc0
May 21, 2016
- AMDGPU: Define priorities for register classes · 7f9eabd2
  Matt Arsenault authored May 21, 2016
  7f9eabd2
- AMDGPU: Fix relationship between SReg_32 and SReg_32_XM0 · 8f5e0085
  Matt Arsenault authored May 21, 2016
  8f5e0085
Apr 29, 2016
- Fixed/Recommitted r267733 "[AMDGPU][llvm-mc] Add support of TTMP quads. Rework... · 38e496b1
  Artem Tamazov authored Apr 29, 2016
  38e496b1
Apr 27, 2016
- Revert "[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD." · 03e1647d
  Chad Rosier authored Apr 27, 2016
  03e1647d
- [AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD. · 3896f8f8
  Artem Tamazov authored Apr 27, 2016
  3896f8f8
Apr 20, 2016
- AMDGPU/SI: Assembler: improvements to support trap handlers. · fb5c307c
  Nikolay Haustov authored Apr 20, 2016
  fb5c307c
Apr 13, 2016
- [AMDGPU][llvm-mc] Support of Trap Handler registers (TTMP0..11 and TBA/TMA)git status · eb4d5a9b
  Artem Tamazov authored Apr 13, 2016
  eb4d5a9b
Feb 13, 2016
- AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions · bc4497b1
  Tom Stellard authored Feb 12, 2016
  bc4497b1
Jan 26, 2016
- AMDGPU: Make v32i8/v64i8 illegal types · c5f61529
  Matt Arsenault authored Jan 26, 2016
  c5f61529
Dec 21, 2015
- AMDGPU/SI: Fix encoding for FLAT_SCRATCH registers on VI · 2b65ed30
  Tom Stellard authored Dec 21, 2015
  2b65ed30