Commits · 865f7fecb28cd517fe2fa104522b71016ba8c77d · Raul Torres / llvm-target-spread · GitLab

Jan 04, 2018
- [ARM GlobalISel] Select G_PHI · 865f7fec
  Diana Picus authored Jan 04, 2018
  865f7fec
- [ARM GlobalISel] Legalize scalar G_PHI · c768bbe2
  Diana Picus authored Jan 04, 2018
  c768bbe2
- [ARM GlobalISel] Fix selection of pointer constants · 37ae9f68
  Diana Picus authored Jan 04, 2018
  37ae9f68
Jan 03, 2018
- [X86] Remove 'else' after 'return' I forgot to cleanup before committing D41691. · e6e9c275
  Craig Topper authored Jan 03, 2018
  e6e9c275
- AMDGPU: Remove dead file · 4ff5e002
  Matt Arsenault authored Jan 03, 2018
  4ff5e002
- [X86] Remove useless custom inserter for 64-bit TAILJMP and TCRETURN opcodes · 8232e88d
  Craig Topper authored Jan 03, 2018
  8232e88d
- [X86] Use ANY_EXTEND instead of SIGN_EXTEND in lowerMasksToReg · cc6637b7
  Craig Topper authored Jan 03, 2018
  cc6637b7
- Remove left-over debug printout from r321692 · 79985490
  Hans Wennborg authored Jan 03, 2018
  79985490
- [ARM][NFC] Avoid recreating MCSubtargetInfo in ARMAsmBackend · 46db78b7
  Alex Bradbury authored Jan 03, 2018
  46db78b7
- [AArch64][SVE] Asm: Add restricted register classes for SVE predicate vectors. · dc5e081b
  Sander de Smalen authored Jan 03, 2018
  dc5e081b
- Fix build of WebAssembly and AVR backends after r321692 · 7c093bf1
  Alex Bradbury authored Jan 03, 2018
  7c093bf1
- Thread MCSubtargetInfo through Target::createMCAsmBackend · b22f751f
  Alex Bradbury authored Jan 03, 2018
  b22f751f
Jan 02, 2018
- Handle the case of live 16-bit subregisters in X86FixupBWInsts · e12e08c6
  Andrew Kaylor authored Jan 02, 2018
  e12e08c6
- [x86] allow pairs of PCMPEQ for vector-sized integer equality comparisons (PR33325) · 9a80871f
  Sanjay Patel authored Jan 02, 2018
  9a80871f
- [AArch64][GlobalISel] Enable GlobalISel at -O0 by default · 854d10d1
  Amara Emerson authored Jan 02, 2018
  854d10d1
- [Hexagon] Fix generation of vector sign extensions · cfe4a361
  Krzysztof Parzyszek authored Jan 02, 2018
  cfe4a361
- [AArch64][AsmParser] Add isScalarReg() and repurpose isReg() · c9b3e1cf
  Sander de Smalen authored Jan 02, 2018
  c9b3e1cf
- Strip trailing whitespace. NFCI · 39f50e10
  Simon Pilgrim authored Jan 02, 2018
  39f50e10
- [RISCV] Add Defs Uses information for c.jal and c.addi4spn · 8cb894b3
  Alex Bradbury authored Jan 02, 2018
  8cb894b3
- [RISCV][NFC] Resolve unused variable warning in RISCVISelLowering · 3633d120
  Alex Bradbury authored Jan 02, 2018
  3633d120
Jan 01, 2018
- [X86] Promote vXi1 fp_to_uint/fp_to_sint to vXi32 to avoid scalarization. · c8898b36
  Craig Topper authored Jan 01, 2018
  c8898b36
- [X86] Replace custom lowering of vXi1 SINT_TO_FP/UINT_TO_FP with promotion. · e5943bb3
  Craig Topper authored Jan 01, 2018
  e5943bb3
- [SelectionDAG][X86][AArch64] Require targets to specify the promotion type... · a4f99976
  Craig Topper authored Jan 01, 2018
  a4f99976
- [X86] In LowerTruncateVecI1, don't add SHL if the input is known to be all sign bits. · 0d35edda
  Craig Topper authored Jan 01, 2018
  0d35edda
- [X86] Add missing NoVLX predicate around some patterns that use zmm registers... · 694c73ad
  Craig Topper authored Jan 01, 2018
  694c73ad
- [X86] Add patterns for using zmm registers for v8i32/v8f32 vselect with the false input being zero. · fc3ce499
  Craig Topper authored Jan 01, 2018
  fc3ce499
Dec 31, 2017
- [X86] Use CONCAT_VECTORS instead of INSERT_SUBVECTOR for padding v4i1/v2i1... · f78b75fb
  Craig Topper authored Dec 31, 2017
  f78b75fb
- [X86][AVX2] Combine extract(broadcast(scalar_value)) --> scalar_value · b0006753
  Simon Pilgrim authored Dec 31, 2017
  b0006753
- [X86][SSE] Don't vectorize splat buildvector of binops (PR30780) · f205ec71
  Simon Pilgrim authored Dec 31, 2017
  f205ec71
- [X86] Add a DAG combine to widen (i4 (bitcast (v4i1))) before type... · f0f6eefb
  Craig Topper authored Dec 31, 2017
  f0f6eefb
- [X86] Add a DAG combine to fix (v4i1 (bitcast (i4))) before type legalization... · 7f396235
  Craig Topper authored Dec 31, 2017
  7f396235
- [X86] Prevent combining (v8i1 (bitconvert (i8 load)))->(v8i1 load) if we don't have DQI. · 876ec0b5
  Craig Topper authored Dec 31, 2017
  876ec0b5
- [X86] Remove patterns for load/store of vXi with bitcasts to/from integer. · 6159f5eb
  Craig Topper authored Dec 31, 2017
  6159f5eb
- [X86] Remove AND32ri8 from pattern for v1i1 load. · a362dee7
  Craig Topper authored Dec 31, 2017
  a362dee7
- [X86] Fix a crash when returning a <1 x i1> value> · 7ba1b768
  Craig Topper authored Dec 31, 2017
  7ba1b768
- [X86] Cleanup store splitting in LowerTruncatingStore · 1d0e2e82
  Craig Topper authored Dec 31, 2017
  1d0e2e82
Dec 30, 2017
- Use phi ranges to simplify code. No functionality change intended. · c7fc81e6
  Benjamin Kramer authored Dec 30, 2017
  c7fc81e6
- [PowerPC] fix a bug in TCO eligibility check · ca3cdd7f
  Hiroshi Inoue authored Dec 30, 2017
  ca3cdd7f
- [X86] Remove isel patterns for kshifts with types that don't support kshift natively. · 97cc7b03
  Craig Topper authored Dec 30, 2017
  97cc7b03
- [X86] Custom legalize vXi1 extract_subvector with KSHIFTR. · c5fd31a8
  Craig Topper authored Dec 30, 2017
  c5fd31a8