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  1. Mar 12, 2019
  2. Mar 11, 2019
    • Sanjoy Das's avatar
      Revert "Relax constraints for reduction vectorization" · 2136a5bc
      Sanjoy Das authored
      This reverts commit r355868.  Breaks hexagon.
      
      llvm-svn: 355873
      2136a5bc
    • Craig Topper's avatar
      [X86] Remove ProcModel and ProcFeatures tablegen classes. Move all feature... · a958d40e
      Craig Topper authored
      [X86] Remove ProcModel and ProcFeatures tablegen classes. Move all feature lists into a ProcessorFeatures class.
      
      ProcFeatures was a class that just concatenated two feature lists together and gave it a name. We used it to inherit features between CPUs.
      
      ProcModel took a two CPU feature lists and concatenated them before deferring to ProcessorModel. This was to allow inherited features and specific features to be passed to each CPU.
      
      Both of these allowed for only very rigid CPU inheritance rules.
      
      With this patch we now store all of the lists we were using for inheritance in one object and do any list oncatenation we want there. Then we just pass whatever list we want from this class into the ProcessorModel class for each CPU.
      
      Hopefully this gives us more flexibility to build up feature lists in whatever ways we think make sense. Perhaps untangling ISA flags and tuning flags.
      
      I've only touched the CPUs that were directly affected by the removal of the ProcModel and ProcFeatures classes. We should move more of the feature lists into ProcessorFeatures.
      
      llvm-svn: 355872
      a958d40e
    • Jessica Paquette's avatar
      Recommit "[GlobalISel][AArch64] Add selection support for G_EXTRACT_VECTOR_ELT" · 607774c9
      Jessica Paquette authored
      After r355865, we should be able to safely select G_EXTRACT_VECTOR_ELT without
      running into any problematic intrinsics.
      
      Also add a fix for lane copies, which don't support index 0.
      
      llvm-svn: 355871
      607774c9
    • Evgeniy Stepanov's avatar
      Remove ASan asm instrumentation. · aedec3f6
      Evgeniy Stepanov authored
      Summary: It is incomplete and has no users AFAIK.
      
      Reviewers: pcc, vitalybuka
      
      Subscribers: srhines, kubamracek, mgorny, krytarowski, eraman, hiraditya, jdoerfert, #sanitizers, llvm-commits, thakis
      
      Tags: #sanitizers, #llvm
      
      Differential Revision: https://reviews.llvm.org/D59154
      
      llvm-svn: 355870
      aedec3f6
    • Alex Bradbury's avatar
      [RISCV] Do a sign-extension in a compare-and-swap of 32 bit in RV64A · 4d20cc21
      Alex Bradbury authored
      AtomicCmpSwapWithSuccess is legalised into an AtomicCmpSwap plus a comparison.
      This requires an extension of the value which, by default, is a
      zero-extension. When we later lower AtomicCmpSwap into a PseudoCmpXchg32 and then expanded in
      RISCVExpandPseudoInsts.cpp, the lr.w instruction does a sign-extension.
      
      This mismatch of extensions causes the comparison to fail when the compared
      value is negative. This change overrides TargetLowering::getExtendForAtomicOps
      for RISC-V so it does a sign-extension instead.
      
      Differential Revision: https://reviews.llvm.org/D58829
      Patch by Ferran Pallarès Roca.
      
      llvm-svn: 355869
      4d20cc21
    • Sanjoy Das's avatar
      Relax constraints for reduction vectorization · 93f8cc18
      Sanjoy Das authored
      Summary:
      Gating vectorizing reductions on *all* fastmath flags seems unnecessary;
      `reassoc` should be sufficient.
      
      Reviewers: tvvikram, mkuper, kristof.beyls, sdesmalen, Ayal
      
      Reviewed By: sdesmalen
      
      Subscribers: dcaballe, huntergr, jmolloy, mcrosier, jlebar, bixia, llvm-commits
      
      Tags: #llvm
      
      Differential Revision: https://reviews.llvm.org/D57728
      
      llvm-svn: 355868
      93f8cc18
    • Alex Bradbury's avatar
      [RISCV] Allow fp as an alias of s0 · b6d322bd
      Alex Bradbury authored
      The RISC-V Assembly Programmer's Manual defines fp as another alias of x8.
      However, our tablegen rules only recognise s0. This patch adds fp as another
      alias of x8. GCC also accepts fp.
      
      Differential Revision: https://reviews.llvm.org/D59209
      Patch by Ferran Pallarès Roca.
      
      llvm-svn: 355867
      b6d322bd
    • Jessica Paquette's avatar
      [GlobalISel][AArch64] Always fall back on aarch64.neon.addp.* · 42d16501
      Jessica Paquette authored
      Overloaded intrinsics aren't necessarily safe for instruction selection. One
      such intrinsic is aarch64.neon.addp.*.
      
      This is a temporary workaround to ensure that we always fall back on that
      intrinsic. Eventually this will be replaced with a proper solution.
      
      https://bugs.llvm.org/show_bug.cgi?id=40968
      
      Differential Revision: https://reviews.llvm.org/D59062
      
      llvm-svn: 355865
      42d16501
    • Alex Bradbury's avatar
      2c6c84e5
    • Nico Weber's avatar
      Remove esan. · 885b790f
      Nico Weber authored
      It hasn't seen active development in years, and it hasn't reached a
      state where it was useful.
      
      Remove the code until someone is interested in working on it again.
      
      Differential Revision: https://reviews.llvm.org/D59133
      
      llvm-svn: 355862
      885b790f
    • Nikita Popov's avatar
      [SDAG][AArch64] Legalize VECREDUCE · aa7cfa75
      Nikita Popov authored
      Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
      
      Implement basic legalizations (PromoteIntRes, PromoteIntOp,
      ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
      There are more legalizations missing (esp float legalizations),
      but there's no way to test them right now, so I'm not adding them.
      
      This also includes a few more changes to make this work somewhat
      reasonably:
      
       * Add support for expanding VECREDUCE in SDAG. Usually
         experimental.vector.reduce is expanded prior to codegen, but if the
         target does have native vector reduce, it may of course still be
         necessary to expand due to legalization issues. This uses a shuffle
         reduction if possible, followed by a naive scalar reduction.
       * Allow the result type of integer VECREDUCE to be larger than the
         vector element type. For example we need to be able to reduce a v8i8
         into an (nominally) i32 result type on AArch64.
       * Use the vector operand type rather than the scalar result type to
         determine the action, so we can control exactly which vector types are
         supported. Also change the legalize vector op code to handle
         operations that only have vector operands, but no vector results, as
         is the case for VECREDUCE.
       * Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
         explicitly specify for which vector types the reductions are supported.
      
      This does not handle anything related to VECREDUCE_STRICT_*.
      
      Differential Revision: https://reviews.llvm.org/D58015
      
      llvm-svn: 355860
      aa7cfa75
    • Jonas Paulsson's avatar
      [RegAlloc] Avoid compile time regression with multiple copy hints. · 8b8dc50e
      Jonas Paulsson authored
      As a fix for https://bugs.llvm.org/show_bug.cgi?id=40986 ("excessive compile
      time building opencollada"), this patch makes sure that no phys reg is hinted
      more than once from getRegAllocationHints().
      
      This handles the case were many virtual registers are assigned to the same
      physreg. The previous compile time fix (r343686) in weightCalcHelper() only
      made sure that physical/virtual registers are passed no more than once to
      addRegAllocationHint().
      
      Review: Dimitry Andric, Quentin Colombet
      https://reviews.llvm.org/D59201
      
      llvm-svn: 355854
      8b8dc50e
    • Brian Gesiak's avatar
      [coroutines][PR40979] Ignore unreachable uses across suspend points · d7b68132
      Brian Gesiak authored
      Summary:
      Depends on https://reviews.llvm.org/D59069.
      
      https://bugs.llvm.org/show_bug.cgi?id=40979 describes a bug in which the
      -coro-split pass would assert that a use was across a suspend point from
      a definition. Normally this would mean that a value would "spill" across
      a suspend point and thus need to be stored in the coroutine frame. However,
      in this case the use was unreachable, and so it would not be necessary
      to store the definition on the frame.
      
      To prevent the assert, simply remove unreachable basic blocks from a
      coroutine function before computing spills. This avoids the assert
      reported in PR40979.
      
      Reviewers: GorNishanov, tks2103
      
      Reviewed By: GorNishanov
      
      Subscribers: EricWF, jdoerfert, llvm-commits, lewissbaker
      
      Tags: #llvm
      
      Differential Revision: https://reviews.llvm.org/D59068
      
      llvm-svn: 355852
      d7b68132
    • Michael Trent's avatar
      Detect malformed LC_LINKER_COMMANDs in Mach-O binaries · 76d66123
      Michael Trent authored
      Summary:
      llvm-objdump can be tricked into reading beyond valid memory and
      segfaulting if LC_LINKER_COMMAND strings are not null terminated. libObject
      does have code to validate the integrity of the LC_LINKER_COMMAND struct,
      but this validator improperly assumes linker command strings are null
      terminated.
      
      The solution is to report an error if a string extends beyond the end of
      the LC_LINKER_COMMAND struct.
      
      Reviewers: lhames, pete
      
      Reviewed By: pete
      
      Subscribers: rupprecht, llvm-commits
      
      Tags: #llvm
      
      Differential Revision: https://reviews.llvm.org/D59179
      
      llvm-svn: 355851
      76d66123
    • Jinsong Ji's avatar
      [NFC][PowerPC] Add comment for PPCAsmPrinter::printOperand · c6063e83
      Jinsong Ji authored
      Patch by Yi-Hong Lyu
      
      llvm-svn: 355848
      c6063e83
    • Simon Pilgrim's avatar
      [DAG] FoldSetCC - reuse valuetype + ensure its simple. · f3be93a2
      Simon Pilgrim authored
      llvm-svn: 355847
      f3be93a2
    • Brian Gesiak's avatar
      [Utils] Extract EliminateUnreachableBlocks (NFC) · 4349dc76
      Brian Gesiak authored
      Summary:
      Extract the functionality of eliminating unreachable basic blocks
      within a function, previously encapsulated within the
      -unreachableblockelim pass, and make it available as a function within
      BlockUtils.h. No functional change intended other than making the logic
      reusable.
      
      Exposing this logic makes it easier to implement
      https://reviews.llvm.org/D59068, which fixes coroutines bug
      https://bugs.llvm.org/show_bug.cgi?id=40979.
      
      Reviewers: mkazantsev, wmi, davidxl, silvas, davide
      
      Reviewed By: davide
      
      Subscribers: llvm-commits
      
      Tags: #llvm
      
      Differential Revision: https://reviews.llvm.org/D59069
      
      llvm-svn: 355846
      4349dc76
    • Simon Pilgrim's avatar
      [DAG] Move SetCC NaN handling into FoldSetCC · 1bb5b564
      Simon Pilgrim authored
      llvm-svn: 355845
      1bb5b564
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