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  1. Oct 14, 2018
  2. Oct 13, 2018
  3. Oct 12, 2018
  4. Oct 11, 2018
    • Leonard Chan's avatar
      [PassManager/Sanitizer] Port of AddresSanitizer pass from legacy to new PassManager · 64e21b5c
      Leonard Chan authored
      This patch ports the legacy pass manager to the new one to take advantage of
      the benefits of the new PM. This involved moving a lot of the declarations for
      `AddressSantizer` to a header so that it can be publicly used via
      PassRegistry.def which I believe contains all the passes managed by the new PM.
      
      This patch essentially decouples the instrumentation from the legacy PM such
      hat it can be used by both legacy and new PM infrastructure.
      
      Differential Revision: https://reviews.llvm.org/D52739
      
      llvm-svn: 344274
      64e21b5c
    • Amara Emerson's avatar
      [InstCombine] Fix SimplifyLibCalls erasing an instruction while IC still had references to it. · 54f60255
      Amara Emerson authored
      InstCombine keeps a worklist and assumes that optimizations don't
      eraseFromParent() the instruction, which SimplifyLibCalls violates. This change
      adds a new callback to SimplifyLibCalls to let clients specify their own hander
      for erasing actions.
      
      Differential Revision: https://reviews.llvm.org/D52729
      
      llvm-svn: 344251
      54f60255
    • David Green's avatar
      [InstCombine] Demand bits of UMin · 80661984
      David Green authored
      This is the umin alternative to the umax code from rL344237. We use
      DeMorgans law on the umax case to bring us to the same thing on umin,
      but using countLeadingOnes, not countLeadingZeros.
      
      Differential Revision: https://reviews.llvm.org/D53036
      
      llvm-svn: 344239
      80661984
    • David Green's avatar
      [InstCombine] Demand bits of UMax · 30c0e98b
      David Green authored
      Use the demanded bits of umax(A,C) to prove we can just use A so long as the
      lowest non-zero bit of DemandMask is higher than the highest non-zero bit of C
      
      Differential Revision: https://reviews.llvm.org/D53033
      
      llvm-svn: 344237
      30c0e98b
    • Florian Hahn's avatar
      [LV] Use SmallVector instead of DenseMap in calculateRegisterUsage (NFC). · 18e07bb8
      Florian Hahn authored
      We assign indices sequentially for seen instructions, so we can just use
      a vector and push back the seen instructions. No need for using a
      DenseMap.
      
      Reviewers: hsaito, rengolin, nadav, dcaballe
      
      Reviewed By: rengolin
      
      Differential Revision: https://reviews.llvm.org/D53089
      
      llvm-svn: 344233
      18e07bb8
    • Florian Hahn's avatar
      [LV] Ignore more debug info. · 7eb5cb4e
      Florian Hahn authored
      We can avoid doing some unnecessary work by skipping debug instructions
      in a few loops. It also helps to ensure debug instructions do not
      prevent vectorization, although I do not have any concrete test cases
      for that.
      
      Reviewers: rengolin, hsaito, dcaballe, aprantl, vsk
      
      Reviewed By: rengolin, dcaballe
      
      Differential Revision: https://reviews.llvm.org/D53091
      
      llvm-svn: 344232
      7eb5cb4e
    • Calixte Denizet's avatar
      [gcov] Display the hit counter for the line of a function definition · d2f290b0
      Calixte Denizet authored
      Summary:
      Right now there is no hit counter on the line of function.
      So the idea is add the line of the function to all the lines covered by the entry block.
      Tests in compiler-rt/profile will be fixed in another patch: https://reviews.llvm.org/D49854
      
      Reviewers: marco-c, davidxl
      
      Reviewed By: marco-c
      
      Subscribers: sylvestre.ledru, llvm-commits
      
      Differential Revision: https://reviews.llvm.org/D49853
      
      llvm-svn: 344228
      d2f290b0
    • Max Kazantsev's avatar
      [IndVars] Drop "exact" flag from lshr and udiv when substituting their args · b2e51090
      Max Kazantsev authored
      There is a transform that may replace `lshr (x+1), 1` with `lshr x, 1` in case
      if it can prove that the result will be the same. However the initial instruction
      might have an `exact` flag set, and it now should be dropped unless we prove
      that it may hold. Incorrectly set `exact` attribute may then produce poison.
      
      Differential Revision: https://reviews.llvm.org/D53061
      Reviewed By: sanjoy
      
      llvm-svn: 344223
      b2e51090
    • Richard Smith's avatar
      Add a flag to remap manglings when reading profile data information. · 6c676628
      Richard Smith authored
      This can be used to preserve profiling information across codebase
      changes that have widespread impact on mangled names, but across which
      most profiling data should still be usable. For example, when switching
      from libstdc++ to libc++, or from the old libstdc++ ABI to the new ABI,
      or even from a 32-bit to a 64-bit build.
      
      The user can provide a remapping file specifying parts of mangled names
      that should be treated as equivalent (eg, std::__1 should be treated as
      equivalent to std::__cxx11), and profile data will be treated as
      applying to a particular function if its name is equivalent to the name
      of a function in the profile data under the provided equivalences. See
      the documentation change for a description of how this is configured.
      
      Remapping is supported for both sample-based profiling and instruction
      profiling. We do not support remapping indirect branch target
      information, but all other profile data should be remapped
      appropriately.
      
      Support is only added for the new pass manager. If someone wants to also
      add support for this for the old pass manager, doing so should be
      straightforward.
      
      This is the LLVM side of Clang r344199.
      
      Reviewers: davidxl, tejohnson, dlj, erik.pilkington
      
      Subscribers: mehdi_amini, steven_wu, dexonsmith, llvm-commits
      
      Differential Revision: https://reviews.llvm.org/D51249
      
      llvm-svn: 344200
      6c676628
  5. Oct 10, 2018
    • George Burgess IV's avatar
      Replace most users of UnknownSize with LocationSize::unknown(); NFC · 6ef8002c
      George Burgess IV authored
      Moving away from UnknownSize is part of the effort to migrate us to
      LocationSizes (e.g. the cleanup promised in D44748).
      
      This doesn't entirely remove all of the uses of UnknownSize; some uses
      require tweaks to assume that UnknownSize isn't just some kind of int.
      This patch is intended to just be a trivial replacement for all places
      where LocationSize::unknown() will Just Work.
      
      llvm-svn: 344186
      6ef8002c
    • Sanjay Patel's avatar
      [InstCombine] reverse 'trunc X to <N x i1>' canonicalization; 2nd try · 05aadf88
      Sanjay Patel authored
      Re-trying r344082 because it unintentionally included extra diffs.
      
      Original commit message:
      icmp ne (and X, 1), 0 --> trunc X to N x i1
      
      Ideally, we'd do the same for scalars, but there will likely be
      regressions unless we add more trunc folds as we're doing here
      for vectors.
      
      The motivating vector case is from PR37549:
      https://bugs.llvm.org/show_bug.cgi?id=37549
      
      define <4 x float> @bitwise_select(<4 x float> %x, <4 x float> %y, <4 x float> %z, <4 x float> %w) {
      
        %c = fcmp ole <4 x float> %x, %y
        %s = sext <4 x i1> %c to <4 x i32>
        %s1 = shufflevector <4 x i32> %s, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
        %s2 = shufflevector <4 x i32> %s, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3>
        %cond = or <4 x i32> %s1, %s2
        %condtr = trunc <4 x i32> %cond to <4 x i1>
        %r = select <4 x i1> %condtr, <4 x float> %z, <4 x float> %w
        ret <4 x float> %r
      
      }
      
      Here's a sampling of the vector codegen for that case using
      mask+icmp (current behavior) vs. trunc (with this patch):
      
      AVX before:
      
      vcmpleps        %xmm1, %xmm0, %xmm0
      vpermilps       $80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
      vpermilps       $250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
      vorps   %xmm0, %xmm1, %xmm0
      vandps  LCPI0_0(%rip), %xmm0, %xmm0
      vxorps  %xmm1, %xmm1, %xmm1
      vpcmpeqd        %xmm1, %xmm0, %xmm0
      vblendvps       %xmm0, %xmm3, %xmm2, %xmm0
      
      AVX after:
      
      vcmpleps        %xmm1, %xmm0, %xmm0
      vpermilps       $80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
      vpermilps       $250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
      vorps   %xmm0, %xmm1, %xmm0
      vblendvps       %xmm0, %xmm2, %xmm3, %xmm0
      
      AVX512f before:
      
      vcmpleps        %xmm1, %xmm0, %xmm0
      vpermilps       $80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
      vpermilps       $250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
      vorps   %xmm0, %xmm1, %xmm0
      vpbroadcastd    LCPI0_0(%rip), %xmm1 ## xmm1 = [1,1,1,1]
      vptestnmd       %zmm1, %zmm0, %k1
      vblendmps       %zmm3, %zmm2, %zmm0 {%k1}
      
      AVX512f after:
      
      vcmpleps        %xmm1, %xmm0, %xmm0
      vpermilps       $80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
      vpermilps       $250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
      vorps   %xmm0, %xmm1, %xmm0
      vpslld  $31, %xmm0, %xmm0
      vptestmd        %zmm0, %zmm0, %k1
      vblendmps       %zmm2, %zmm3, %zmm0 {%k1}
      
      AArch64 before:
      
      fcmge   v0.4s, v1.4s, v0.4s
      zip1    v1.4s, v0.4s, v0.4s
      zip2    v0.4s, v0.4s, v0.4s
      orr     v0.16b, v1.16b, v0.16b
      movi    v1.4s, #1
      and     v0.16b, v0.16b, v1.16b
      cmeq    v0.4s, v0.4s, #0
      bsl     v0.16b, v3.16b, v2.16b
      
      AArch64 after:
      
      fcmge   v0.4s, v1.4s, v0.4s
      zip1    v1.4s, v0.4s, v0.4s
      zip2    v0.4s, v0.4s, v0.4s
      orr     v0.16b, v1.16b, v0.16b
      bsl     v0.16b, v2.16b, v3.16b
      
      PowerPC-le before:
      
      xvcmpgesp 34, 35, 34
      vspltisw 0, 1
      vmrglw 3, 2, 2
      vmrghw 2, 2, 2
      xxlor 0, 35, 34
      xxlxor 35, 35, 35
      xxland 34, 0, 32
      vcmpequw 2, 2, 3
      xxsel 34, 36, 37, 34
      
      PowerPC-le after:
      
      xvcmpgesp 34, 35, 34
      vmrglw 3, 2, 2
      vmrghw 2, 2, 2
      xxlor 0, 35, 34
      xxsel 34, 37, 36, 0
      
      Differential Revision: https://reviews.llvm.org/D52747
      
      llvm-svn: 344181
      05aadf88
    • Sanjay Patel's avatar
      revert r344082: [InstCombine] reverse 'trunc X to <N x i1>' canonicalization · 58fc00d0
      Sanjay Patel authored
      This commit accidentally included the diffs from D53057.
      
      llvm-svn: 344178
      58fc00d0
    • Renato Golin's avatar
      [VPlan] Fix CondBit quoting in dumpBasicBlock · d8e7ca4a
      Renato Golin authored
      Quotes were being printed for VPInstructions but not the rest.
      
      llvm-svn: 344161
      d8e7ca4a
    • Scott Linder's avatar
      Relax trivial cast requirements in CallPromotionUtils · 3759efc6
      Scott Linder authored
      Differential Revision: https://reviews.llvm.org/D52792
      
      llvm-svn: 344153
      3759efc6
    • Carlos Alberto Enciso's avatar
      Revert "[DebugInfo][Dexter] Unreachable line stepped onto after SimplifyCFG." · c0952c8a
      Carlos Alberto Enciso authored
      This reverts commit r344120.
      
      It was causing buildbot failures.
      
      llvm-svn: 344135
      c0952c8a
    • Neil Henning's avatar
      Fix an ordering bug in the scalarizer. · 3d457982
      Neil Henning authored
      I've added a new test case that causes the scalarizer to try and use
      dead-and-erased values - caused by the basic blocks not being in
      domination order within the function. To fix this, instead of iterating
      through the blocks in function order, I walk them in reverse post order.
      
      Differential Revision: https://reviews.llvm.org/D52540
      
      llvm-svn: 344128
      3d457982
    • Carlos Alberto Enciso's avatar
      [DebugInfo][Dexter] Unreachable line stepped onto after SimplifyCFG. · e7a347e5
      Carlos Alberto Enciso authored
      When SimplifyCFG changes the PHI node into a select instruction, the debug line records becomes ambiguous. It causes the debugger to display unreachable source lines. 
      
      Differential Revision: https://reviews.llvm.org/D52887
      
      llvm-svn: 344120
      e7a347e5
    • George Burgess IV's avatar
      [Analysis] Make LocationSizes carry an 'imprecise' bit · 40dc63e1
      George Burgess IV authored
      There are places where we need to merge multiple LocationSizes of
      different sizes into one, and get a sensible result.
      
      There are other places where we want to optimize aggressively based on
      the value of a LocationSizes (e.g. how can a store of four bytes be to
      an area of storage that's only two bytes large?)
      
      This patch makes LocationSize hold an 'imprecise' bit to note whether
      the LocationSize can be treated as an upper-bound and lower-bound for
      the size of a location, or just an upper-bound.
      
      This concludes the series of patches leading up to this. The most recent
      of which is r344108.
      
      Fixes PR36228.
      
      Differential Revision: https://reviews.llvm.org/D44748
      
      llvm-svn: 344114
      40dc63e1
    • Max Kazantsev's avatar
      [NFC] Make a variable const · 1d893bfc
      Max Kazantsev authored
      llvm-svn: 344113
      1d893bfc
  6. Oct 09, 2018
    • Sanjay Patel's avatar
      [InstCombine] reverse 'trunc X to <N x i1>' canonicalization · e9ca7ea3
      Sanjay Patel authored
      icmp ne (and X, 1), 0 --> trunc X to N x i1
      
      Ideally, we'd do the same for scalars, but there will likely be 
      regressions unless we add more trunc folds as we're doing here 
      for vectors.
      
      The motivating vector case is from PR37549:
      https://bugs.llvm.org/show_bug.cgi?id=37549
      
      define <4 x float> @bitwise_select(<4 x float> %x, <4 x float> %y, <4 x float> %z, <4 x float> %w) {
        %c = fcmp ole <4 x float> %x, %y
        %s = sext <4 x i1> %c to <4 x i32>
        %s1 = shufflevector <4 x i32> %s, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
        %s2 = shufflevector <4 x i32> %s, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3>
        %cond = or <4 x i32> %s1, %s2
        %condtr = trunc <4 x i32> %cond to <4 x i1>
        %r = select <4 x i1> %condtr, <4 x float> %z, <4 x float> %w
        ret <4 x float> %r
      }
      
      Here's a sampling of the vector codegen for that case using 
      mask+icmp (current behavior) vs. trunc (with this patch):
      
      AVX before:
      
      vcmpleps	%xmm1, %xmm0, %xmm0
      vpermilps	$80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
      vpermilps	$250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
      vorps	%xmm0, %xmm1, %xmm0
      vandps	LCPI0_0(%rip), %xmm0, %xmm0
      vxorps	%xmm1, %xmm1, %xmm1
      vpcmpeqd	%xmm1, %xmm0, %xmm0
      vblendvps	%xmm0, %xmm3, %xmm2, %xmm0
      
      AVX after:
      
      vcmpleps	%xmm1, %xmm0, %xmm0
      vpermilps	$80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
      vpermilps	$250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
      vorps	%xmm0, %xmm1, %xmm0
      vblendvps	%xmm0, %xmm2, %xmm3, %xmm0
      
      AVX512f before:
      
      vcmpleps	%xmm1, %xmm0, %xmm0
      vpermilps	$80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
      vpermilps	$250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
      vorps	%xmm0, %xmm1, %xmm0
      vpbroadcastd	LCPI0_0(%rip), %xmm1 ## xmm1 = [1,1,1,1]
      vptestnmd	%zmm1, %zmm0, %k1
      vblendmps	%zmm3, %zmm2, %zmm0 {%k1}
      
      AVX512f after:
      
      vcmpleps	%xmm1, %xmm0, %xmm0
      vpermilps	$80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
      vpermilps	$250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
      vorps	%xmm0, %xmm1, %xmm0
      vpslld	$31, %xmm0, %xmm0
      vptestmd	%zmm0, %zmm0, %k1
      vblendmps	%zmm2, %zmm3, %zmm0 {%k1}
      
      AArch64 before:
      
      fcmge	v0.4s, v1.4s, v0.4s
      zip1	v1.4s, v0.4s, v0.4s
      zip2	v0.4s, v0.4s, v0.4s
      orr	v0.16b, v1.16b, v0.16b
      movi	v1.4s, #1
      and	v0.16b, v0.16b, v1.16b
      cmeq	v0.4s, v0.4s, #0
      bsl	v0.16b, v3.16b, v2.16b
      
      AArch64 after:
      
      fcmge	v0.4s, v1.4s, v0.4s
      zip1	v1.4s, v0.4s, v0.4s
      zip2	v0.4s, v0.4s, v0.4s
      orr	v0.16b, v1.16b, v0.16b
      bsl	v0.16b, v2.16b, v3.16b
      
      PowerPC-le before:
      
      xvcmpgesp 34, 35, 34
      vspltisw 0, 1
      vmrglw 3, 2, 2
      vmrghw 2, 2, 2
      xxlor 0, 35, 34
      xxlxor 35, 35, 35
      xxland 34, 0, 32
      vcmpequw 2, 2, 3
      xxsel 34, 36, 37, 34
      
      PowerPC-le after:
      
      xvcmpgesp 34, 35, 34
      vmrglw 3, 2, 2
      vmrghw 2, 2, 2
      xxlor 0, 35, 34
      xxsel 34, 37, 36, 0
      
      Differential Revision: https://reviews.llvm.org/D52747
      
      llvm-svn: 344082
      e9ca7ea3
    • Sanjay Patel's avatar
      [InstCombine] make helper function 'static'; NFC · 88194dfe
      Sanjay Patel authored
      llvm-svn: 344056
      88194dfe
    • George Burgess IV's avatar
      Make LocationSize a proper Optional type; NFC · f96e6180
      George Burgess IV authored
      This is the second in a series of changes intended to make
      https://reviews.llvm.org/D44748 more easily reviewable. Please see that
      patch for more context. The first change being r344012.
      
      Since I was requested to do all of this with post-commit review, this is
      about as small as I can make this patch.
      
      This patch makes LocationSize into an actual type that wraps a uint64_t;
      users are required to call getValue() in order to get the size now. If
      the LocationSize has an Unknown size (e.g. if LocSize ==
      MemoryLocation::UnknownSize), getValue() will assert.
      
      This also adds DenseMap specializations for LocationInfo, which required
      taking two more values from the set of values LocationInfo can
      represent. Hence, heavy users of multi-exabyte arrays or structs may
      observe slightly lower-quality code as a result of this change.
      
      The intent is for getValue()s to be very close to a corresponding
      hasValue() (which is often spelled `!= MemoryLocation::UnknownSize`).
      Sadly, small diff context appears to crop that out sometimes, and the
      last change in DSE does require a bit of nonlocal reasoning about
      control-flow. :/
      
      This also removes an assert, since it's now redundant with the assert in
      getValue().
      
      llvm-svn: 344013
      f96e6180
    • George Burgess IV's avatar
      Use locals instead of struct fields; NFC · fefc42c9
      George Burgess IV authored
      This is one of a series of changes intended to make
      https://reviews.llvm.org/D44748 more easily reviewable. Please see that
      patch for more context.
      
      Since I was requested to do all of this with post-commit review, this is
      about as small as I can make it (beyond committing changes to these few
      files separately, but they're incredibly similar in spirit, so...)
      
      On its own, this change doesn't make a great deal of sense. I plan on
      having a follow-up Real Soon Now(TM) to make the bits here make more
      sense. :)
      
      In particular, the next change in this series is meant to make
      LocationSize an actual type, which you have to call .getValue() on in
      order to get at the uint64_t inside. Hence, this change refactors code
      so that:
      - we only need to call the soon-to-come getValue() once in most cases,
        and
      - said call to getValue() happens very closely to a piece of code that
        checks if the LocationSize has a value (e.g. if it's != UnknownSize).
      
      llvm-svn: 344012
      fefc42c9
  7. Oct 08, 2018
    • Robert Lougher's avatar
      [TailCallElim] Enable marking of calls with byval as tails · 0c93ea26
      Robert Lougher authored
      In r339636 the alias analysis rules were changed with regards to tail calls
      and byval arguments. Previously, tail calls were assumed not to alias
      allocas from the current frame. This has been updated, to not assume this
      for arguments with the byval attribute.
      
      This patch aligns TailCallElim with the new rule. Tail marking can now be
      more aggressive and mark more calls as tails, e.g.:
      
      define void @test() {
        %f = alloca %struct.foo
        call void @bar(%struct.foo* byval %f)
        ret void
      }
      
      define void @test2(%struct.foo* byval %f) {
        call void @bar(%struct.foo* byval %f)
        ret void
      }
      
      define void @test3(%struct.foo* byval %f) {
        %agg.tmp = alloca %struct.foo
        %0 = bitcast %struct.foo* %agg.tmp to i8*
        %1 = bitcast %struct.foo* %f to i8*
        call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 40, i1 false)
        call void @bar(%struct.foo* byval %agg.tmp)
        ret void
      }
      
      The problematic case where a byval parameter is captured by a call is still
      handled correctly, and will not be marked as a tail (see PR7272).
      
      llvm-svn: 343986
      0c93ea26
    • Xin Tong's avatar
      [ThinLTO] Keep non-prevailing (linkonce|weak)_odr symbols live · bfdad33b
      Xin Tong authored
      Summary:
      If we have a symbol with (linkonce|weak)_odr linkage, we do not want
      to dead strip it even it is not prevailing.
      
      IR level (linkonce|weak)_odr symbol can become non-prevailing when we mix
      ELF objects and IR objects where the (linkonce|weak)_odr symbol in the ELF
      object is prevailing and the ones in the IR objects are not. Stripping
      them will prevent us from doing optimizations with them.
      
      By not dead stripping them, We will convert these symbols to
      available_externally linkage as a result of non-prevailing and eventually
      dropping them after inlining.
      
      I modified cache-prevailing.ll to use linkonce linkage as it is
      testing whether cache prevailing bit is effective or not, not
      we should treat linkonce_odr alive or not
      
      Reviewers: tejohnson, pcc
      
      Subscribers: mehdi_amini, inglorion, eraman, steven_wu, dexonsmith, llvm-commits
      
      Differential Revision: https://reviews.llvm.org/D52893
      
      llvm-svn: 343970
      bfdad33b
    • Neil Henning's avatar
      [IRBuilder] Fixup CreateIntrinsic to allow specifying Types to Mangle. · 57f5d0a8
      Neil Henning authored
      The IRBuilder CreateIntrinsic method wouldn't allow you to specify the
      types that you wanted the intrinsic to be mangled with. To fix this
      I've:
      
      - Added an ArrayRef<Type *> member to both CreateIntrinsic overloads.
      - Used that array to pass into the Intrinsic::getDeclaration call.
      - Added a CreateUnaryIntrinsic to replace the most common use of
        CreateIntrinsic where the type was auto-deduced from operand 0.
      - Added a bunch more unit tests to test Create*Intrinsic calls that
        weren't being tested (including the FMF flag that wasn't checked).
      
      This was suggested as part of the AMDGPU specific atomic optimizer
      review (https://reviews.llvm.org/D51969).
      
      Differential Revision: https://reviews.llvm.org/D52087
      
      llvm-svn: 343962
      57f5d0a8
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