Commits · 572f45a3c857dfbacd16d792176435331d1825ac · Lorenzo Albano / LLVM bpEVL · GitLab

Aug 28, 2017
- Create PHI node for the return value only when the return value has uses. · 572f45a3
  Taewook Oh authored Aug 28, 2017
  572f45a3
- [CodeView] Don't output S_UDT symbols for forward decls. · a7b04174
  Zachary Turner authored Aug 28, 2017
  a7b04174
- [Power9] Add new instructions for floating point status and control registers. · c35e4de3
  Stefan Pintilie authored Aug 28, 2017
  c35e4de3
- [InstCombine] Call hasNoSignedWrap instead of hasNoUnsignedWrap to get the NSW... · 3763f0e0
  Craig Topper authored Aug 28, 2017
  3763f0e0
- [Hexagon] Check for potential bank conflicts in post-RA scheduling · 2164a271
  Krzysztof Parzyszek authored Aug 28, 2017
  2164a271
- [AMDGPU] Fix regression in AMDGPULibCalls allowing native for doubles · 312c557b
  Stanislav Mekhanoshin authored Aug 28, 2017
  312c557b
- [AMDGPU] computeKnownBitsForTargetNode for 24 bit mul · dad7cf62
  Stanislav Mekhanoshin authored Aug 28, 2017
  dad7cf62
- [Hexagon] Break up DAG mutations into separate classes, move to subtarget · 95da97ec
  Krzysztof Parzyszek authored Aug 28, 2017
  95da97ec
- [Hexagon] Move pre-RA DAG mutations to scheduler constructor · 697297af
  Krzysztof Parzyszek authored Aug 28, 2017
  697297af
- [X86] Make 128/256-bit extract_subvector Legal instead of Custom. Move... · fa86fd92
  Craig Topper authored Aug 28, 2017
  fa86fd92
- [DAGCombiner] Teach visitEXTRACT_SUBVECTOR to turn extracts of BUILD_VECTOR... · 029a21df
  Craig Topper authored Aug 28, 2017
  029a21df
- The current version of LLVM X86 disassembler incorrectly interprets some... · 574962a3
  Andrew V. Tischenko authored Aug 28, 2017
  574962a3
- [X86][Haswell] Updating HSW instruction scheduling information · d76f7b82
  Gadi Haber authored Aug 28, 2017
  d76f7b82
- Untabify. · a1e97a77
  NAKAMURA Takumi authored Aug 28, 2017
  a1e97a77
- [X86] Use getUnpackl helper to create an ISD::VECTOR_SHUFFLE instead of using... · 33681161
  Craig Topper authored Aug 28, 2017
  33681161
- [X86] Add an early out to combineLoopMAddPattern and combineLoopSADPattern when SSE2 is disabled. · 2c77011d
  Craig Topper authored Aug 28, 2017
  2c77011d
- revert r310985 which breaks for the following case: · 191b24d3
  Dehao Chen authored Aug 27, 2017
  191b24d3
Aug 27, 2017
- [mips] Generate NMADD and NMSUB instructions when fneg node is present · f11daad1
  Petar Jovanovic authored Aug 27, 2017
  f11daad1
- [ARM] Tidy-up condition-code support functions · b81fa993
  Javed Absar authored Aug 27, 2017
  b81fa993
- [AVX512] Add more patterns for using masked moves for subvector extracts of... · 80075a5f
  Craig Topper authored Aug 27, 2017
  80075a5f
- [DAGCombiner] allow undef shuffle operands when eliminating bitcasts (PR34111) · a7a61d97
  Sanjay Patel authored Aug 27, 2017
  a7a61d97
- [ARM] Tidy-up ARMAsmParser. NFC. · 17ee7c09
  Javed Absar authored Aug 27, 2017
  17ee7c09
- [LV] Fix PR34248 - recommit D32871 after revert r311304 · 1f58dda4
  Ayal Zaks authored Aug 27, 2017
  1f58dda4
- [X86] Add a target-specific DAG combine to combine extract_subvector from all... · 36bd247f
  Craig Topper authored Aug 27, 2017
  36bd247f
- [X86] Use getOnesVector instead of using DAG.getConstant(-1). · 71dab64a
  Craig Topper authored Aug 27, 2017
  71dab64a
- [NewGVN] Use `auto` when the type is obvious NFCI. · 9bdccb37
  Davide Italiano authored Aug 26, 2017
  9bdccb37
- [AVX512] Add patterns to match masked extract_subvector with bitcasts between... · a088362e
  Craig Topper authored Aug 26, 2017
  a088362e
Aug 26, 2017
- [Dominators] Remove redundant explicit template instantiation. · a67e1312
  Don Hinton authored Aug 26, 2017
  a67e1312
- [DAGCombiner] Extending pattern detection for vector shuffle. · e4ca95d6
  Jatin Bhateja authored Aug 26, 2017
  e4ca95d6
- Revert rL311247 : To rectify commit message. · b60cfbef
  Jatin Bhateja authored Aug 26, 2017
  b60cfbef
- NewGVN: Fix PR33204 - We need to add memory users when we bypass memorydefs... · de269f46
  Daniel Berlin authored Aug 26, 2017
  de269f46
- [X86] Qualify the RMW INC/DEC patterns with NotSlowIncDec. · 69ec2018
  Craig Topper authored Aug 26, 2017
  69ec2018
- Add options to dump block frequency/branch probability info in text. · 63e17ebf
  Hiroshi Yamauchi authored Aug 26, 2017
  63e17ebf
- [AVX512] Add patterns to use masked moves to implement masked... · d27386a9
  Craig Topper authored Aug 25, 2017
  d27386a9
- [x86] Teach the backend to fold more read-modify-write memory operands · 4b611a89
  Chandler Carruth authored Aug 25, 2017
  4b611a89
- [Verifier] Diagnose invalid DIType references instead of crashing. · 26053818
  Davide Italiano authored Aug 25, 2017
  26053818
- [Inliner] Only compute fully inline cost when remarks are enabled. · a872519d
  Davide Italiano authored Aug 25, 2017
  a872519d
- Revert "[SanitizeCoverage] Enable stack-depth coverage for -fsanitize=fuzzer" · 6ec7595b
  Matt Morehouse authored Aug 25, 2017
  6ec7595b
Aug 25, 2017
- [SanitizeCoverage] Enable stack-depth coverage for -fsanitize=fuzzer · f42bd313
  Matt Morehouse authored Aug 25, 2017
  f42bd313
- [sanitizer-coverage] extend fsanitize-coverage=pc-table with flags for every PC · d3e4b7e2
  Kostya Serebryany authored Aug 25, 2017
  d3e4b7e2