Commits · 5c38ca35346f3aa8c04dc827a403c6ec605d8acc · Lorenzo Albano / LLVM bpEVL · GitLab

Aug 16, 2019
- [SDAG] Minor code cleanup/standardization of atomic accessors [NFC] · 5c38ca35
  Philip Reames authored Aug 15, 2019
  5c38ca35
- Add missing MIR serialization text for AArch64II::MO_TAGGED. · 10ce5f88
  Evgeniy Stepanov authored Aug 15, 2019
  10ce5f88
Aug 15, 2019
- Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM · 0c476111
  Daniel Sanders authored Aug 15, 2019
  0c476111
- [Hexagon] Fix instruction selection for vselect v4i8 · 8e987702
  Krzysztof Parzyszek authored Aug 15, 2019
  8e987702
- MVT: Add v3i16/v3f16 vectors · 1f2b7272
  Matt Arsenault authored Aug 15, 2019
  1f2b7272
- [X86] Add custom type legalization for bitcasting mmx to v2i32/v4i16/v8i8 to... · 2a372ba5
  Craig Topper authored Aug 15, 2019
  2a372ba5
- [X86] Improve cost model for subvector extraction of less than 128-bit vectors · 6eebd2bc
  Craig Topper authored Aug 15, 2019
  6eebd2bc
- [Hexagon] Generate vector min/max for HVX · 8460301d
  Krzysztof Parzyszek authored Aug 15, 2019
  8460301d
- [llvm] Migrate llvm::make_unique to std::make_unique · 0eaee545
  Jonas Devlieghere authored Aug 15, 2019
  0eaee545
- [PowerPC] Use xxleqv to set all one vector IMM(-1). · 9fd81dc1
  Jinsong Ji authored Aug 15, 2019
  9fd81dc1
- [ARM] Fix alignment checks for BE VLDRH · 3a991018
  David Green authored Aug 15, 2019
  3a991018
- [SDAG][x86] check for relaxed math when matching an FP reduction · 57d45930
  Sanjay Patel authored Aug 15, 2019
  57d45930
- [ARM] MVE predicate store patterns · 0ff2296a
  David Green authored Aug 15, 2019
  0ff2296a
- [AArch64] Change location of frame-record within callee-save area. · 643adb55
  Sander de Smalen authored Aug 15, 2019
  643adb55
- [ARM] MVE trunc to i1 vectors · 04f2f328
  David Green authored Aug 15, 2019
  04f2f328
- [X86] Add isel pattern to match VZEXT_MOVL and a v2i64 scalar_to_vector... · 1e246b20
  Craig Topper authored Aug 15, 2019
  1e246b20
- [X86] Make sure load is non-volatile in the MMX_X86movdq2q (loadv2i64) isel pattern. · e6409602
  Craig Topper authored Aug 15, 2019
  e6409602
- [X86] Remove unneeded isel pattern for v4f32->v4i32 fp_to_sint and conversion to MMX. · dbcbbf56
  Craig Topper authored Aug 15, 2019
  dbcbbf56
- [X86] Disable custom type legalization for v2i32/v4i16/v8i8->i64. · a57734ba
  Craig Topper authored Aug 15, 2019
  a57734ba
- [X86] Disable custom type legalization for v2i32/v4i16/v8i8->f64 bitcast. · 57286afe
  Craig Topper authored Aug 15, 2019
  57286afe
- [X86] Remove some unreachable code from LowerBITCAST. · ba39fcd8
  Craig Topper authored Aug 15, 2019
  ba39fcd8
- [X86] Remove some dead code and combine some repeated code that's left. · 14f75600
  Craig Topper authored Aug 15, 2019
  14f75600
Aug 14, 2019
- [AArch64][GlobalISel] Custom selection for s8 load acquire. · 1222cfd5
  Amara Emerson authored Aug 14, 2019
  1222cfd5
- InferAddressSpaces: Move target intrinsic handling to TTI · dbc1f207
  Matt Arsenault authored Aug 14, 2019
  dbc1f207
- [WebAssembly] Stop unrolling SIMD shifts since they are fixed in V8 · de0133ea
  Thomas Lively authored Aug 14, 2019
  de0133ea
- [X86] Use PSADBW for v8i8 addition reductions. · 3e44d961
  Craig Topper authored Aug 14, 2019
  3e44d961
- [NFC][AIX] Change assertion · 49661f94
  Xiangling Liao authored Aug 14, 2019
  49661f94
- [X86][CostModel] Adjust the costs of ZERO_EXTEND/SIGN_EXTEND with less than 128-bit inputs · 30d3e9c3
  Craig Topper authored Aug 14, 2019
  30d3e9c3
- [X86] Add llvm_unreachable to a switch that covers all expected values. · 8c545168
  Craig Topper authored Aug 14, 2019
  8c545168
- [PowerPC][NFC] Consolidate duplicate XX3Form_SetZero and XX3Form_Zero. · e71db658
  Jinsong Ji authored Aug 14, 2019
  e71db658
- [AIX] Add call lowering for parameters that could pass onto FPRs · 8fc095d4
  Jason Liu authored Aug 14, 2019
  8fc095d4
- [AArch64][GlobalISel] RBS: Treat s128s like vectors when unmerging. · 2a312fc9
  Amara Emerson authored Aug 13, 2019
  2a312fc9
- [AArch64] Remove incorrect usage of MONonTemporal. · b5eb3e1e
  Eli Friedman authored Aug 13, 2019
  b5eb3e1e
Aug 13, 2019
- [AIX]Lowering global address for 32/64bit small/large code models · a8c624a1
  Xiangling Liao authored Aug 13, 2019
  a8c624a1
- [AMDGPU] Fix to 'Fold readlane from copy of SGPR or imm' · 10db641a
  Tim Renouf authored Aug 13, 2019
  10db641a
- [ARM] Add MVE beats vector cost model · a655393f
  David Green authored Aug 13, 2019
  a655393f
- Use Register over unsigned in LateEHPrepare (NFC) · 64517a64
  Heejin Ahn authored Aug 13, 2019
  64517a64
- Reland r368691: "[AIX] Implement LR prolog/epilog save/restore" · 09967050
  Hubert Tong authored Aug 13, 2019
  09967050
- GlobalISel: Partially implement fewerElementsVector G_UNMERGE_VALUES · 28215caa
  Matt Arsenault authored Aug 13, 2019
  28215caa
- [ARM] Fix detection of duplicates when parsing reg list operands · 114c37e7
  Momchil Velikov authored Aug 13, 2019
  114c37e7