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  1. Jul 09, 2018
    • Stefan Pintilie's avatar
      [Power9] Add __float128 builtins for Round To Odd · 83a5fe14
      Stefan Pintilie authored
      GCC has builtins for these round to odd instructions:
      
      __float128 __builtin_sqrtf128_round_to_odd (__float128)
      __float128 __builtin_{add,sub,mul,div}f128_round_to_odd (__float128, __float128)
      __float128 __builtin_fmaf128_round_to_odd (__float128, __float128, __float128)
      
      Differential Revision: https://reviews.llvm.org/D47550
      
      llvm-svn: 336578
      83a5fe14
    • Maksim Panchenko's avatar
      [DebugInfo] Change default value of FDEPointerEncoding · fa762cc1
      Maksim Panchenko authored
      Summary:
      If the encoding is not specified in CIE augmentation string, then it
      should be DW_EH_PE_absptr instead of DW_EH_PE_omit.
      
      Reviewers: ruiu, MaskRay, plotfi, rafauler
      
      Reviewed By: MaskRay
      
      Subscribers: rafauler, JDevlieghere, llvm-commits
      
      Differential Revision: https://reviews.llvm.org/D49000
      
      llvm-svn: 336577
      fa762cc1
    • Craig Topper's avatar
      [SelectionDAG] Add VT consistency checks to the creation of ISD::FMA. · e3b0c7e5
      Craig Topper authored
      This is similar to what is done for binops. I don't know if this would have helped us catch the bug fixed in r336566 earlier or not, but I figured it couldn't hurt.
      
      llvm-svn: 336576
      e3b0c7e5
    • Jonathan Peyton's avatar
      [OpenMP] Fix a few formatting issues · 61d44f18
      Jonathan Peyton authored
      llvm-svn: 336575
      61d44f18
    • Steven Wu's avatar
      Add bitcode compatibility test for 6.0 · a1a8e66a
      Steven Wu authored
      Summary:
      Add bitcode compatibility test for 6.0. On top of the normal disassemble
      test, also runs the verifier to make sure simple 6.0 bitcode can pass
      the current IR verifier.
      
      Reviewers: vsk
      
      Reviewed By: vsk
      
      Subscribers: dexonsmith, llvm-commits
      
      Differential Revision: https://reviews.llvm.org/D49086
      
      llvm-svn: 336574
      a1a8e66a
    • Alex Shlyapnikov's avatar
      [ASan] Minor ASan error reporting cleanup · 63af9157
      Alex Shlyapnikov authored
      Summary:
      - use proper Error() decorator for error messages
      - refactor ASan thread id and name reporting
      
      Reviewers: eugenis
      
      Subscribers: kubamracek, delcypher, #sanitizers, llvm-commits
      
      Differential Revision: https://reviews.llvm.org/D49044
      
      llvm-svn: 336573
      63af9157
    • Diego Caballero's avatar
      [LoopInfo] Port loop exit interfaces from Loop to LoopBase · 29a07b37
      Diego Caballero authored
      This patch ports hasDedicatedExits, getUniqueExitBlocks and
      getUniqueExitBlock in Loop to LoopBase so that they can be used
      from other LoopBase sub-classes.
      
      Reviewers: chandlerc, sanjoy, hfinkel, fhahn
      
      Reviewed By: chandlerc
      
      Differential Revision: https://reviews.llvm.org/D48817
      
      llvm-svn: 336572
      29a07b37
    • Jonathan Peyton's avatar
      [OpenMP] Introduce hierarchical scheduling · f6399367
      Jonathan Peyton authored
      This patch introduces the logic implementing hierarchical scheduling.
      First and foremost, hierarchical scheduling is off by default
      To enable, use -DLIBOMP_USE_HIER_SCHED=On during CMake's configure stage.
      This work is based off if the IWOMP paper:
      "Workstealing and Nested Parallelism in SMP Systems"
      
      Hierarchical scheduling is the layering of OpenMP schedules for different layers
      of the memory hierarchy. One can have multiple layers between the threads and
      the global iterations space. The threads will go up the hierarchy to grab
      iterations, using possibly a different schedule & chunk for each layer.
      
      [ Global iteration space (0-999) ]
      
      (use static)
      [ L1 | L1 | L1 | L1 ]
      
      (use dynamic,1)
      [ T0 T1 | T2 T3 | T4 T5 | T6 T7 ]
      
      In the example shown above, there are 8 threads and 4 L1 caches begin targeted.
      If the topology indicates that there are two threads per core, then two
      consecutive threads will share the data of one L1 cache unit. This example
      would have the iteration space (0-999) split statically across the four L1
      caches (so the first L1 would get (0-249), the second would get (250-499), etc).
      Then the threads will use a dynamic,1 schedule to grab iterations from the L1
      cache units. There are currently four supported layers: L1, L2, L3, NUMA
      
      OMP_SCHEDULE can now read a hierarchical schedule with this syntax:
      OMP_SCHEDULE='EXPERIMENTAL LAYER,SCHED[,CHUNK][:LAYER,SCHED[,CHUNK]...]:SCHED,CHUNK
      And OMP_SCHEDULE can still read the normal SCHED,CHUNK syntax from before
      
      I've kept most of the hierarchical scheduling logic inside kmp_dispatch_hier.h
      to try to keep it separate from the rest of the code.
      
      Differential Revision: https://reviews.llvm.org/D47962
      
      llvm-svn: 336571
      f6399367
    • Sanjay Patel's avatar
      [InstCombine] correct test comments; NFC · 651438c2
      Sanjay Patel authored
      llvm-svn: 336570
      651438c2
    • Alexey Bataev's avatar
      [OPENMP, NVPTX] Support several images in the executable. · 2622e9e5
      Alexey Bataev authored
      Summary:
      Currently Cuda plugin supports loading of the single image, though we
      may have the executable with the several images, if it has target
      regions inside of the dynamically loaded library. Patch allows to load
      multiple images.
      
      Reviewers: grokos
      
      Subscribers: guansong, openmp-commits, kkwli0
      
      Differential Revision: https://reviews.llvm.org/D49036
      
      llvm-svn: 336569
      2622e9e5
    • Jonathan Peyton's avatar
      [OpenMP] Restructure loop code for hierarchical scheduling · 39ada854
      Jonathan Peyton authored
      This patch reorganizes the loop scheduling code in order to allow hierarchical
      scheduling to use it more effectively. In particular, the goal of this patch
      is to separate the algorithmic parts of the scheduling from the thread
      logistics code.
      
      Moves declarations & structures to kmp_dispatch.h for easier access in
      other files.  Extracts the algorithmic part of __kmp_dispatch_init() and
      __kmp_dispatch_next() into __kmp_dispatch_init_algorithm() and
      __kmp_dispatch_next_algorithm(). The thread bookkeeping logic is still kept in
      __kmp_dispatch_init() and __kmp_dispatch_next(). This is done because the
      hierarchical scheduler needs to access the scheduling logic without the
      bookkeeping logic.  To prepare for new pointer in dispatch_private_info_t, a
      new flags variable is created which stores the ordered and nomerge flags instead
      of them being in two separate variables. This will keep the
      dispatch_private_info_t structure the same size.
      
      Differential Revision: https://reviews.llvm.org/D47961
      
      llvm-svn: 336568
      39ada854
    • Alexey Bataev's avatar
      [OPENMP, NVPTX] Do not globalize local variables in parallel regions. · b99dcb5f
      Alexey Bataev authored
      In generic data-sharing mode we are allowed to not globalize local
      variables that escape their declaration context iff they are declared
      inside of the parallel region. We can do this because L2 parallel
      regions are executed sequentially and, thus, we do not need to put
      shared local variables in the global memory.
      
      llvm-svn: 336567
      b99dcb5f
    • Craig Topper's avatar
      [X86] In combineFMA, make sure we bitcast the result of isFNEG back the... · 47170b31
      Craig Topper authored
      [X86] In combineFMA, make sure we bitcast the result of isFNEG back the expected type before creating the new FMA node.
      
      Previously, we were creating malformed SDNodes, but nothing noticed because the type constraints prevented isel from noticing.
      
      llvm-svn: 336566
      47170b31
    • Simon Pilgrim's avatar
      [X86][AVX] Regenerate AVX1 fast-isel tests. · d0706592
      Simon Pilgrim authored
      Let the update script merge 32/64 tests where possible
      
      llvm-svn: 336565
      d0706592
    • Stella Stamenova's avatar
      Retrieve a function PDB symbol correctly from nested blocks · 67a19dfb
      Stella Stamenova authored
      Summary:
      This patch fixes a problem with retrieving a function symbol by an address in a nested block. In the current implementation of ResolveSymbolContext function it retrieves a symbol with PDB_SymType::None and then checks if found symbol's tag equals to PDB_SymType::Function. So, if nested block's symbol was found, ResolveSymbolContext does not resolve a function.
      
      It is very simple to reproduce this. For example, in the next program
      
      ```
      int main() {
        auto r = 0;
        for (auto i = 1; i <= 10; i++) {
          r += i & 1 + (i - 1) & 1 - 1;
        }
      
        return r;
      }
      ```
      
      if we will stop inside the cycle and will do a backtrace, the top element will be broken. But how we can test this? I thought to add an option to lldb-test to allow search a function by address, but the address may change when the compiler will be changed.
      
      Patch by: Aleksandr Urakov
      
      Reviewers: asmith, labath, zturner
      
      Reviewed By: asmith, labath
      
      Subscribers: stella.stamenova, llvm-commits
      
      Differential Revision: https://reviews.llvm.org/D47939
      
      llvm-svn: 336564
      67a19dfb
    • Jonathan Peyton's avatar
      [OpenMP] Use C++11 Atomics - barrier, tasking, and lock code · 37e2ef54
      Jonathan Peyton authored
      These are preliminary changes that attempt to use C++11 Atomics in the runtime.
      We are expecting better portability with this change across architectures/OSes.
      Here is the summary of the changes.
      
      Most variables that need synchronization operation were converted to generic
      atomic variables (std::atomic<T>). Variables that are updated with combined CAS
      are packed into a single atomic variable, and partial read/write is done
      through unpacking/packing
      
      Patch by Hansang Bae
      
      Differential Revision: https://reviews.llvm.org/D47903
      
      llvm-svn: 336563
      37e2ef54
    • Sanjay Patel's avatar
      [InstCombine] avoid extra poison when moving shift above shuffle · 7cd32419
      Sanjay Patel authored
      As discussed in D49047 / D48987, shift-by-undef produces poison,
      so we can't use undef vector elements in that case..
      
      Note that we need to extend this for poison-generating flags,
      and there's a proposal to create poison from FMF in D47963,
      
      llvm-svn: 336562
      7cd32419
    • Jonas Devlieghere's avatar
      [dsymutil] Add support for outputting assembly · 82dee6ac
      Jonas Devlieghere authored
      When implementing the DWARF accelerator tables in dsymutil I ran into an
      assertion in the assembler. Debugging these kind of issues is a lot
      easier when looking at the assembly instead of debugging the assembler
      itself. Since it's only a matter of creating an AsmStreamer instead of a
      MCObjectStreamer it made sense to turn this into a (hidden) dsymutil
      feature.
      
      Differential revision: https://reviews.llvm.org/D49079
      
      llvm-svn: 336561
      82dee6ac
    • Steven Wu's avatar
      [BitcodeReader] Infer the correct runtime preemption for GlobalValue · e1f7c5f8
      Steven Wu authored
      Summary:
      To allow bitcode built by old compiler to pass the current verifer,
      BitcodeReader needs to auto infer the correct runtime preemption from
      linkage and visibility for GlobalValues.
      
      Since llvm-6.0 bitcode already contains the new field but can be
      incorrect in some cases, the attribute needs to be recomputed all the
      time in BitcodeReader. This will make all the GVs has dso_local marked
      correctly if read from bitcode, and it should still allow the verifier
      to catch mistakes in optimization passes.
      
      This should fix PR38009.
      
      Reviewers: sfertile, vsk
      
      Reviewed By: vsk
      
      Subscribers: dexonsmith, llvm-commits
      
      Differential Revision: https://reviews.llvm.org/D49039
      
      llvm-svn: 336560
      e1f7c5f8
    • Zaara Syeda's avatar
      [PPC64] Add TLS local dynamic to local exec relaxation · 75c348a0
      Zaara Syeda authored
      This patch adds the target call back relaxTlsLdToLe to support TLS relaxation
      from local dynamic to local exec model.
      
      Differential Revision: https://reviews.llvm.org/D48293
      
      llvm-svn: 336559
      75c348a0
    • Sanjay Patel's avatar
      [InstCombine] generalize safe vector constant utility · a6272531
      Sanjay Patel authored
      This is almost NFC, but there could be some case where the original
      code had undefs in the constants (rather than just the shuffle mask),
      and we'll use safe constants rather than undefs now.
      
      The FIXME noted in foldShuffledBinop() is already visible in existing
      tests, so correcting that is the next step.
      
      llvm-svn: 336558
      a6272531
    • Craig Topper's avatar
      [X86] Remove some patterns that include a bitcast of a floating point load to an integer type. · e9cff7d4
      Craig Topper authored
      DAG combine should have converted the type of the load.
      
      llvm-svn: 336557
      e9cff7d4
    • Craig Topper's avatar
      [X86] Remove some patterns that seems to be unreachable. · 16ee4b49
      Craig Topper authored
      These patterns mapped (v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))) to a MOVSD and an zeroing XOR. But the complexity of a pattern for (v2f64 (X86vzmovl (v2f64))) that selects MOVQ is artificially and hides this MOVSD pattern.
      
      Weirder still, the SSE version of the pattern was explicitly blocked on SSE41, but yet we had copied it to AVX and AVX512.
      
      llvm-svn: 336556
      16ee4b49
    • Craig Topper's avatar
      [X86] Remove some seemingly unnecessary AddedComplexity lines. · 22330c70
      Craig Topper authored
      Looking at the generated tables this didn't seem to make an obvious difference in pattern priority.
      
      llvm-svn: 336555
      22330c70
    • Diego Caballero's avatar
      [VPlan][LV] Introduce condition bit in VPBlockBase · d0953014
      Diego Caballero authored
      This patch introduces a VPValue in VPBlockBase to represent the condition
      bit that is used as successor selector when a block has multiple successors.
      This information wasn't necessary until now, when we are about to introduce
      outer loop vectorization support in VPlan code gen.
      
      Reviewers: fhahn, rengolin, mkuper, hfinkel, mssimpso
      
      Reviewed By: fhahn
      
      Differential Revision: https://reviews.llvm.org/D48814
      
      llvm-svn: 336554
      d0953014
    • Eric Liu's avatar
      [clangd] Support indexing MACROs. · 48db19e9
      Eric Liu authored
      Summary: This is not enabled in the global-symbol-builder or dynamic index yet.
      
      Reviewers: sammccall
      
      Reviewed By: sammccall
      
      Subscribers: ilya-biryukov, MaskRay, jkorous, cfe-commits
      
      Differential Revision: https://reviews.llvm.org/D49028
      
      llvm-svn: 336553
      48db19e9
    • Sander de Smalen's avatar
      [AArch64][SVE] Asm: Support for CNT(B|H|W|D) and CNTP instructions. · d3efb59f
      Sander de Smalen authored
      This patch adds support for the following instructions:
      
        CNTB CNTH - Determine the number of active elements implied by
        CNTW CNTD   the named predicate constant, multiplied by an
                    immediate, e.g.
      
                      cnth x0, vl8, #16
      
        CNTP      - Count active predicate elements, e.g.
                      cntp  x0, p0, p1.b
      
                    counts the number of active elements in p1, predicated
                    by p0, and stores the result in x0.
      
      llvm-svn: 336552
      d3efb59f
    • Xin Tong's avatar
      [CVP] Handle calls with void return value. No need to create CVPLattice state for it. · b467233d
      Xin Tong authored
      Summary:
      Tests: 10
      Metric: compile_time
      
      Program                                         unpatch-result  patch-result diff
      
      Bullet/bullet                                  32.39           30.54        -5.7%
      SPASS/SPASS                                    18.14           17.25        -4.9%
      mafft/pairlocalalign                           12.10           11.64        -3.8%
      ClamAV/clamscan                                19.21           19.63         2.2%
      7zip/7zip-benchmark                            49.55           48.85        -1.4%
      kimwitu++/kc                                   15.68           15.87         1.2%
      lencod/lencod                                  21.13           21.34         1.0%
      consumer-typeset/consumer-typeset              13.65           13.62        -0.2%
      tramp3d-v4/tramp3d-v4                          29.88           29.92         0.1%
      sqlite3/sqlite3                                18.48           18.46        -0.1%
             unpatch-result  patch-result       diff
      count  10.000000       10.000000     10.000000
      mean   23.022000       22.712400    -0.011671
      std    11.362831       11.094183     0.027338
      min    12.104000       11.640000    -0.057298
      25%    16.299000       16.214000    -0.032282
      50%    18.844000       19.048000    -0.001350
      75%    27.689000       27.774000     0.007752
      max    49.552000       48.852000     0.021861
      
      I also tested only this pass by concatenating all the code from the
      llvm/lib/Analysis/ folder and do clang -g followed by opt. I get close to 20% speedup
      for the pass. I expect a majority of the gain come from skipping the dbg intrinsics.
      
      Before patch (opt -time-passes -called-value-propagation):
      ============
      ===-------------------------------------------------------------------------===
       ... Pass execution timing report ...
      ===-------------------------------------------------------------------------===
       Total Execution Time: 3.8303 seconds (3.8279 wall clock)
      
       ---User Time--- --System Time-- --User+System-- ---Wall Time--- ---
      Name ---
       2.0768 ( 57.3%) 0.0990 ( 48.0%) 2.1757 ( 56.8%) 2.1757 ( 56.8%) Bitcode
      Writer
       0.8444 ( 23.3%) 0.0600 ( 29.1%) 0.9044 ( 23.6%) 0.9044 ( 23.6%) Called
      Value Propagation
       0.7031 ( 19.4%) 0.0472 ( 22.9%) 0.7502 ( 19.6%) 0.7478 ( 19.5%) Module
      Verifier
       3.6242 (100.0%) 0.2062 (100.0%) 3.8303 (100.0%) 3.8279 (100.0%) Total
      
      After patch (opt -time-passes -called-value-propagation):
      ============
      ===-------------------------------------------------------------------------===
       ... Pass execution timing report ...
      ===-------------------------------------------------------------------------===
       Total Execution Time: 3.6605 seconds (3.6579 wall clock)
      
       ---User Time--- --System Time-- --User+System-- ---Wall Time--- ---
      Name ---
       2.0716 ( 59.7%) 0.0990 ( 52.5%) 2.1705 ( 59.3%) 2.1706 ( 59.3%) Bitcode
      Writer
       0.7144 ( 20.6%) 0.0300 ( 15.9%) 0.7444 ( 20.3%) 0.7444 ( 20.4%) Called
      Value Propagation
       0.6859 ( 19.8%) 0.0596 ( 31.6%) 0.7455 ( 20.4%) 0.7429 ( 20.3%) Module
      Verifier
       3.4719 (100.0%) 0.1886 (100.0%) 3.6605 (100.0%) 3.6579 (100.0%) Total
      
      Reviewers: davide, mssimpso
      
      Subscribers: llvm-commits
      
      Differential Revision: https://reviews.llvm.org/D49078
      
      llvm-svn: 336551
      b467233d
    • Marc-Andre Laperle's avatar
      [clangd] Mark "Document Symbols" as implemented in the docs · 3ff329f6
      Marc-Andre Laperle authored
      Summary: Signed-off-by: Marc-Andre Laperle <marc-andre.laperle@ericsson.com>
      
      Subscribers: ilya-biryukov, ioeric, MaskRay, jkorous, cfe-commits
      
      Differential Revision: https://reviews.llvm.org/D48996
      
      llvm-svn: 336550
      3ff329f6
    • Sam McCall's avatar
      [clangd] Remove JSON library in favor of llvm/Support/JSON · d20d7989
      Sam McCall authored
      Summary:
      The library has graduated from clangd to llvm/Support.
      This is a mechanical change to move to the new API and remove the old one.
      
      Main API changes:
       - namespace clang::clangd::json --> llvm::json
       - json::Expr --> json::Value
       - Expr::asString() etc --> Value::getAsString() etc
       - unsigned longs need a cast (due to r336541 adding lossless integer support)
      
      Reviewers: ilya-biryukov
      
      Subscribers: mgorny, ioeric, MaskRay, jkorous, omtcyfz, cfe-commits
      
      Differential Revision: https://reviews.llvm.org/D49077
      
      llvm-svn: 336549
      d20d7989
    • Stefan Pintilie's avatar
      [Power9] Add __float128 support for compare operations · 3d76326d
      Stefan Pintilie authored
      Added handling for the select f128.
      
      Differential Revision: https://reviews.llvm.org/D48294
      
      llvm-svn: 336548
      3d76326d
    • Sander de Smalen's avatar
      [AArch64][SVE] Asm: Support for remaining shift instructions. · 813b21e3
      Sander de Smalen authored
      This patch completes support for shifts, which include:
      - LSL   - Logical Shift Left
      - LSLR  - Logical Shift Left, Reversed form
      - LSR   - Logical Shift Right
      - LSRR  - Logical Shift Right, Reversed form
      - ASR   - Arithmetic Shift Right
      - ASRR  - Arithmetic Shift Right, Reversed form
      - ASRD  - Arithmetic Shift Right for Divide
      
      In the following variants:
      
      - Predicated shift by immediate - ASR, LSL, LSR, ASRD
        e.g.
          asr z0.h, p0/m, z0.h, #1
      
        (active lanes of z0 shifted by #1)
      
      - Unpredicated shift by immediate - ASR, LSL*, LSR*
        e.g.
          asr z0.h, z1.h, #1
      
        (all lanes of z1 shifted by #1, stored in z0)
      
      - Predicated shift by vector - ASR, LSL*, LSR*
        e.g.
          asr z0.h, p0/m, z0.h, z1.h
      
        (active lanes of z0 shifted by z1, stored in z0)
      
      - Predicated shift by vector, reversed form - ASRR, LSLR, LSRR
        e.g.
          lslr z0.h, p0/m, z0.h, z1.h
      
        (active lanes of z1 shifted by z0, stored in z0)
      
      - Predicated shift left/right by wide vector - ASR, LSL, LSR
        e.g.
          lsl z0.h, p0/m, z0.h, z1.d
      
        (active lanes of z0 shifted by wide elements of vector z1)
      
      - Unpredicated shift left/right by wide vector - ASR, LSL, LSR
        e.g.
          lsl z0.h, z1.h, z2.d
      
        (all lanes of z1 shifted by wide elements of z2, stored in z0)
      
      *Variants added in previous patches.
      
      llvm-svn: 336547
      813b21e3
    • Sanjay Patel's avatar
      [InstCombine] fix shuffle-of-binops transform to avoid poison/undef · 5bd36644
      Sanjay Patel authored
      As noted in D48987, there are many different ways for this transform to go wrong. 
      In particular, the poison potential for shifts means we have to more careful with those ops. 
      I added tests to make that behavior visible for all of the different cases that I could find.
      
      This is a partial fix. To make this review easier, I did not make changes for the single binop 
      pattern (handled in foldSelectShuffleWith1Binop()). I also left out some potential optimizations 
      noted with TODO comments. I'll follow-up once we're confident that things are correct here.
      
      The goal is to correct all marked FIXME tests to either avoid the shuffle transform or do it safely.
      
      Note that distinguishing when the shuffle mask contains undefs and using getBinOpIdentity() allows 
      for some improvements to div/rem patterns, so there are wins along with the missed opportunities 
      and fixes.
      
      Differential Revision: https://reviews.llvm.org/D49047
      
      llvm-svn: 336546
      5bd36644
    • Stefan Maksimovic's avatar
      [mips] Addition of the [d]rem and [d]remu instructions · 0a23998f
      Stefan Maksimovic authored
      Related to http://reviews.llvm.org/D15772
      Depends on http://reviews.llvm.org/D16889
      Adds [D]REM[U] instructions.
      
      Patch By: Srdjan Obucina
      Contributions from: Simon Dardis
      
      Differential Revision: https://reviews.llvm.org/D17036
      
      llvm-svn: 336545
      0a23998f
    • Sander de Smalen's avatar
      [AArch64][SVE] Asm: Support for TBL instruction. · 54077dcf
      Sander de Smalen authored
      Support for SVE's TBL instruction for programmable table
      lookup/permute using vector of element indices, e.g.
      
        tbl  z0.d, { z1.d }, z2.d
      
      stores elements from z1, indexed by elements from z2, into z0.
      
      llvm-svn: 336544
      54077dcf
    • Andrea Di Biagio's avatar
      [llvm-mca] report an error if the assembly sequence contains an unsupported instruction. · 88347796
      Andrea Di Biagio authored
      This is a short-term fix for PR38093.
      For now, we llvm::report_fatal_error if the instruction builder finds an
      unsupported instruction in the instruction stream.
      
      We need to revisit this fix once we start addressing PR38101.
      Essentially, we need a better framework for error handling.
      
      llvm-svn: 336543
      88347796
    • Sam McCall's avatar
      [Support] Allow JSON serialization of Optional<T> for supported T. · 7e4234fc
      Sam McCall authored
      This is ported from r333881 to JSON's new home.
      
      llvm-svn: 336542
      7e4234fc
    • Sam McCall's avatar
      [Support] Make JSON handle doubles and int64s losslessly · d93eaeb7
      Sam McCall authored
      Summary:
      This patch adds a new "integer" ValueType, and renames Number -> Double.
      This allows us to preserve the full precision of int64_t when parsing integers
      from the wire, or constructing from an integer.
      The API is unchanged, other than giving asInteger() a clearer contract.
      
      In addition, always output doubles with enough precision that parsing will
      reconstruct the same double.
      
      Reviewers: simon_tatham
      
      Subscribers: llvm-commits
      
      Differential Revision: https://reviews.llvm.org/D46209
      
      llvm-svn: 336541
      d93eaeb7
    • Ilya Biryukov's avatar
      [clangd] Do not write comments into Preamble PCH · 6f33b330
      Ilya Biryukov authored
      Summary:
      To avoid wasting time deserializing them on code completion and
      further reparses.
      
      We do not use the comments anyway, because we cannot rely on the file
      contents staying the same for reparses that reuse the prebuilt
      preamble PCH.
      
      Reviewers: sammccall
      
      Reviewed By: sammccall
      
      Subscribers: ioeric, MaskRay, jkorous, cfe-commits
      
      Differential Revision: https://reviews.llvm.org/D48943
      
      llvm-svn: 336540
      6f33b330
    • Ilya Biryukov's avatar
      [PCH] Add an option to not write comments into PCH · 45643106
      Ilya Biryukov authored
      Summary:
      Will be used in clangd, see the follow-up change.
      Clangd does not use comments read from PCH to avoid crashes due to
      changed contents of the file. However, reading them considerably slows
      down code completion on files with large preambles.
      
      Reviewers: sammccall
      
      Reviewed By: sammccall
      
      Subscribers: ioeric, cfe-commits
      
      Differential Revision: https://reviews.llvm.org/D48942
      
      llvm-svn: 336539
      45643106
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