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  1. Jan 18, 2020
    • Matt Arsenault's avatar
      Consolidate internal denormal flushing controls · a4451d88
      Matt Arsenault authored
      Currently there are 4 different mechanisms for controlling denormal
      flushing behavior, and about as many equivalent frontend controls.
      
      - AMDGPU uses the fp32-denormals and fp64-f16-denormals subtarget features
      - NVPTX uses the nvptx-f32ftz attribute
      - ARM directly uses the denormal-fp-math attribute
      - Other targets indirectly use denormal-fp-math in one DAGCombine
      - cl-denorms-are-zero has a corresponding denorms-are-zero attribute
      
      AMDGPU wants a distinct control for f32 flushing from f16/f64, and as
      far as I can tell the same is true for NVPTX (based on the attribute
      name).
      
      Work on consolidating these into the denormal-fp-math attribute, and a
      new type specific denormal-fp-math-f32 variant. Only ARM seems to
      support the two different flush modes, so this is overkill for the
      other use cases. Ideally we would error on the unsupported
      positive-zero mode on other targets from somewhere.
      
      Move the logic for selecting the flush mode into the compiler driver,
      instead of handling it in cc1. denormal-fp-math/denormal-fp-math-f32
      are now both cc1 flags, but denormal-fp-math-f32 is not yet exposed as
      a user flag.
      
      -cl-denorms-are-zero, -fcuda-flush-denormals-to-zero and
      -fno-cuda-flush-denormals-to-zero will be mapped to
      -fp-denormal-math-f32=ieee or preserve-sign rather than the old
      attributes.
      
      Stop emitting the denorms-are-zero attribute for the OpenCL flag. It
      has no in-tree users. The meaning would also be target dependent, such
      as the AMDGPU choice to treat this as only meaning allow flushing of
      f32 and not f16 or f64. The naming is also potentially confusing,
      since DAZ in other contexts refers to instructions implicitly treating
      input denormals as zero, not necessarily flushing output denormals to
      zero.
      
      This also does not attempt to change the behavior for the current
      attribute. The LangRef now states that the default is ieee behavior,
      but this is inaccurate for the current implementation. The clang
      handling is slightly hacky to avoid touching the existing
      denormal-fp-math uses. Fixing this will be left for a future patch.
      
      AMDGPU is still using the subtarget feature to control the denormal
      mode, but the new attribute are now emitted. A future change will
      switch this and remove the subtarget features.
      a4451d88
    • Richard Smith's avatar
      Remove redundant CXXScopeSpec from TemplateIdAnnotation. · a42fd84c
      Richard Smith authored
      A TemplateIdAnnotation represents only a template-id, not a
      nested-name-specifier plus a template-id. Don't make a redundant copy of
      the CXXScopeSpec and store it on the template-id annotation.
      
      This slightly improves error recovery by more properly handling the case
      where we would form an invalid CXXScopeSpec while parsing a typename
      specifier, instead of accidentally putting the token stream into a
      broken "annot_template_id with a scope specifier, but with no preceding
      annot_cxxscope token" state.
      a42fd84c
    • Petr Hosek's avatar
      [profile] Support counter relocation at runtime · d3db13af
      Petr Hosek authored
      This is an alternative to the continous mode that was implemented in
      D68351. This mode relies on padding and the ability to mmap a file over
      the existing mapping which is generally only available on POSIX systems
      and isn't suitable for other platforms.
      
      This change instead introduces the ability to relocate counters at
      runtime using a level of indirection. On every counter access, we add a
      bias to the counter address. This bias is stored in a symbol that's
      provided by the profile runtime and is initially set to zero, meaning no
      relocation. The runtime can mmap the profile into memory at abitrary
      location, and set bias to the offset between the original and the new
      counter location, at which point every subsequent counter access will be
      to the new location, which allows updating profile directly akin to the
      continous mode.
      
      The advantage of this implementation is that doesn't require any special
      OS support. The disadvantage is the extra overhead due to additional
      instructions required for each counter access (overhead both in terms of
      binary size and performance) plus duplication of counters (i.e. one copy
      in the binary itself and another copy that's mmapped).
      
      Differential Revision: https://reviews.llvm.org/D69740
      d3db13af
  2. Jan 17, 2020
  3. Jan 16, 2020
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