llvm-svn: 27501

- Normalize shuffle nodes so result vector lower half elements come from the
  first vector, the rest come from the second vector. (Except for the
  exceptions :-).
- Other minor fixes.

llvm-svn: 27474

llvm-svn: 27444

vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>

This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.

It would match a {p}unpckl on x86.

llvm-svn: 27437

llvm-svn: 27434

llvm-svn: 27433

llvm-svn: 27427

Use movhpd to: store upper f64 extracted from v2f64.

llvm-svn: 27382

- Some bug fixes and naming inconsistency fixes.

llvm-svn: 27377

INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.

llvm-svn: 27314

from a 128-bit vector.

llvm-svn: 27304

llvm-svn: 27275

llvm-svn: 27272

llvm-svn: 27271

Use pshufd, pshuhw, and pshulw to shuffle v4f32 if shufps doesn't match.
Use shufps to shuffle v4f32 if pshufd, pshuhw, and pshulw don't match.

llvm-svn: 27259

- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.

llvm-svn: 27252

vector_shuffle undef.

llvm-svn: 27250

- Whenever possible use ops of the right packed types for vector shuffles /
  splats.

llvm-svn: 27246

- Other shuffle related fixes.

llvm-svn: 27244

llvm-svn: 27239

llvm-svn: 27223

llvm-svn: 27222

* Bug fixes.

llvm-svn: 27218

- Some misc. bug fixes.
- Use MOVHPDrm to load from m64 to upper half of a XMM register.

llvm-svn: 27210

intrinsics as such.

llvm-svn: 27200

llvm-svn: 27167

manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks.  The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.

This functionality is currently only enabled on x86, but should be safe for
every target.  In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.

llvm-svn: 27156

llvm-svn: 27150

series of unpack and interleave ops.

llvm-svn: 27119

llvm-svn: 27096

llvm-svn: 27091

llvm-svn: 27056

llvm-svn: 27049

llvm-svn: 27044

llvm-svn: 27040

llvm-svn: 27024

llvm-svn: 26997

llvm-svn: 26967

64-bit vector shuffle.

llvm-svn: 26964

llvm-svn: 26957