as setcc and select next.

llvm-svn: 23295

llvm-svn: 23294

only add a reload live range once for the instruction.  This is one step
towards fixing a regalloc pessimization that Nate notice, but is later undone
by the spiller (so no code is changed).

llvm-svn: 23293

llvm-svn: 23278

as well as fixing how we replace old values with new values.

llvm-svn: 23260

preserve livevar

llvm-svn: 23259

This restores all of stanford to being identical with and without the dag
combiner with the add folding turned off in sd.cpp.

llvm-svn: 23258

we were losing a node, causing an assertion to fail.  Now we eagerly delete
discovered CSE's, and provide an optional vector to keep track of these
discovered equivalences.

llvm-svn: 23255

that option for PowerPC's beta.

llvm-svn: 23253

I have run so far when run before Legalize.  It still needs to pick up the
SetCC folds, and nodes that use SetCC.

llvm-svn: 23243

llvm-svn: 23235

values, and then we should be able to hook it up.

llvm-svn: 23231

llvm-svn: 23229

i64 values on targets that need that expanded to 32-bit registers.  This fixes
PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll and speeds up 189.lucas from
taking 122.72s to 81.96s on my desktop.

llvm-svn: 23228

llvm-svn: 23224

from the binary ops map, even if they had multiple results.  This latent bug
caused a few failures with the dag isel last night.

To prevent stuff like this from happening in the future, add some really
strict checking to make sure that the CSE maps always match up with reality!

llvm-svn: 23221

number of elements.

llvm-svn: 23219

llvm-svn: 23215

llvm-svn: 23208

llvm-svn: 23206

instead of ZERO_EXTEND to eliminate extraneous extensions.  This eliminates
dead zero extensions on formal arguments and other cases on PPC, implementing
the newly tightened up test/Regression/CodeGen/PowerPC/small-arguments.ll test.

llvm-svn: 23205

llvm-svn: 23204

llvm-svn: 23203

over to DAGCombiner.cpp

1. Don't assume that SetCC returns i1 when folding (xor (setcc) constant)
2. Don't duplicate code in folding AND with AssertZext that is handled by
   MaskedValueIsZero

llvm-svn: 23196

left to do).

llvm-svn: 23195

llvm-svn: 23186

statement in visit().

llvm-svn: 23185

be mostly functional.  It currently has all folds from SelectionDAG.cpp
that do not involve a condition code.

llvm-svn: 23184

llvm-svn: 23181

llvm-svn: 23173

llvm-svn: 23169

llvm-svn: 23166

case in MaskedValueIsZero was wrong.

llvm-svn: 23165

MaskedValueIsZero.

llvm-svn: 23164

Allow physregs to occur in the dag with multiple types.  Though I don't likethis, it is a requirement on PPC, which can have an f32 value in r3 at onepoint in a function and a f64 value in r3 at another point.  :(

This fixes compilation of mesa

llvm-svn: 23161

This fixes PR621 and Regression/CodeGen/X86/2005-08-30-RegAllocAliasProblem.ll

llvm-svn: 23158

to SHIFT_PARTS nodes

llvm-svn: 23151

at least tends to expose problems elsewhere.

llvm-svn: 23149

llvm-svn: 23148

them.  This allows for elminination of redundant extends in the entry
blocks of functions on PowerPC.

Add support for i32 x i32 -> i64 multiplies, by recognizing when the inputs
to ISD::MUL in ExpandOp are actually just extended i32 values and not real
i64 values.  this allows us to codegen

int mulhs(int a, int b) { return ((long long)a * b) >> 32; }
as:
_mulhs:
        mulhw r3, r4, r3
        blr

instead of:
_mulhs:
        mulhwu r2, r4, r3
        srawi r5, r3, 31
        mullw r5, r4, r5
        add r2, r2, r5
        srawi r4, r4, 31
        mullw r3, r4, r3
        add r3, r2, r3
        blr

with a similar improvement on x86.

llvm-svn: 23147