on the memcpy call will pull up other unrelated stuff. Fixes PR11142.

llvm-svn: 142150

llvm-svn: 142141

While at it, merge some format strings.

llvm-svn: 142140

llvm-svn: 142139

<stdin>:1:12: error: register %rax is only available in 64-bit mode
   incl    %rax
           ^~~~

llvm-svn: 142137

X86AsmParser: Synthesize EndLoc for tokens out of StartLoc + Length and print ranges for invalid operands.

<stdin>:1:4: error: invalid instruction mnemonic 'abc'
   abc incl    %edi
   ^~~

llvm-svn: 142135

This reenables proper inline asm diagnostics in clang

llvm-svn: 142132

no pattern.

llvm-svn: 142130

llvm-svn: 142122

Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.

llvm-svn: 142117

These missing flags show up as errors when running -verify-coalescing on
test-suite.

llvm-svn: 142111

llvm-svn: 142110

llvm-svn: 142108

string, pass it around as an enum.

llvm-svn: 142107

the X86 asmparser to produce ranges in the one case that was annoying me, for example:

test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
              ^~~~~~~

It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use 
ranges where appropriate if someone is interested.

llvm-svn: 142106

Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen

llvm-svn: 142105

Add X86 feature detection support for BMI instructions. Added new cpuid function for accessing leafs with sub leafs specified in ECX. Also added code to keep track of the max cpuid level supported in both basic and extended leaves and qualified the existing cpuid calls and the new call to leaf 7.

llvm-svn: 142089

Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.

llvm-svn: 142082

The CELL backend cannot select patterns for  vector trunc-store and shl on v2i64; CellSPU/shift_ops.ll fails when promoting elements.

llvm-svn: 142081

llvm-svn: 142080

llvm-svn: 142073

use can't be dominated, saving one domtree lookup.

llvm-svn: 142066

Based on Horspool's simplified version of Boyer-Moore. We use a constant-sized table of
uint8_ts to keep cache thrashing low, needles bigger than 255 bytes are uncommon anyways.

The worst case is still O(n*m) but we do a lot better on the average case now.

llvm-svn: 142061

cases we need the second type-legalization pass in order to support all cases.

llvm-svn: 142060

Just because we're dealing with a GEP doesn't mean we can assert the
SCEV has a pointer type. The fix is simply to ignore the SCEV pointer
type, which we really didn't need.
Fixes PR11138 webkit crash.

llvm-svn: 142058

It extremely breaks builds when optimization is enabled. Twine should not hold temporary objects.

By the way, I might feel sad if I saw "i786-" "i1586-" or "iF86-".

llvm-svn: 142055

from config.h, it discovers the triple based on the execution environment.

Patch by Aaron Ballman <aaron@aaronballman.com>

llvm-svn: 142046

Windows/Memory.inc: Support the ability to allocate memory "near" another block of memory on Win32. It has fixed FIXME.

Thanks to Aaron Ballman!

llvm-svn: 142039

I rewrote the algorithm a while back so it doesn't require map lookup,
but neglected to change the data structure. This was caught by
llvm-gcc self host, not because there's anything special about
llvm-gcc, but because it is the only test for nondeterminism we
currently have. Unit tests don't work well for everything; we should
always try to have a nondeterminism stress test running.

Fixes PR11133: llvm-gcc self host .o mismatch after enable-iv-rewrite=false

llvm-svn: 142036

This isn't put into the 'clear()' method because the information needs to stick
around (at least for a little bit) after the selection DAG is built.

llvm-svn: 142032

It really doesn't, but when r141929 removed the hasSideEffects flag from
this instruction, it caused miscompilations.  I am guessing that it got
moved across a stack pointer update.

Also clear isRematerializable after checking that this instruction is
in fact never rematerialized in the nightly test suite.

llvm-svn: 142030

rdar://10288916 is tracking this fix.

In the past, instcombine and other passes were promoting alloca alignment past
the natural alignment, resulting in dynamic stack realignment.  Lang's work now
prevents this from happening (LLVM commit r141599).  Now that this really 
shouldn't happen report a fatal error rather than silently generate bad code.

llvm-svn: 142028

llvm-svn: 142027

llvm-svn: 142022

llvm-svn: 142021

The callee-saved registers cannot be live across an invoke call because the
control flow may continue along the exceptional edge. When this happens, all of
the callee-saved registers are no longer valid.

llvm-svn: 142018

llvm-svn: 142013

llvm-svn: 142010

    assert("bad SymbolicOp.VariantKind");
To:
    assert(0 && "bad SymbolicOp.VariantKind");

llvm-svn: 142000

llvm-svn: 141990