llvm-svn: 102654

solution.  The only reason these don't fire with gcc-4.2 is that gcc turns off
part of -Wsign-compare in C++ on accident.

llvm-svn: 100581

llvm-svn: 100532

llvm-svn: 99879

llvm-svn: 99637

llvm-svn: 98295

Move methods out of line and M-x whitespace-cleanup.
Promote common method arguments to member variables.

llvm-svn: 98207

Russell Wallace.

llvm-svn: 96580

When coalescing with a physreg, remember to add imp-def and imp-kill when
dealing with sub-registers.

Also fix a related bug in VirtRegRewriter where substitutePhysReg may
reallocate the operand list on an instruction and invalidate the reg_iterator.
This can happen when a register is mentioned twice on the same instruction.

llvm-svn: 96072

llvm-svn: 95748

llvm-svn: 95745

into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687

An instruction like this:

  %reg1097:1<def> = VMOVSR %R3<kill>, 14, %reg0

Must be replaced with this when substituting physical registers:

  %S0<def> = VMOVSR %R3<kill>, 14, %reg0, %D0<imp-def>

llvm-svn: 92812

llvm-svn: 92590

Patch by Howard Hinnant!

llvm-svn: 90365

Fix debug code that assumes getBasicBlock never returns NULL.

llvm-svn: 89428

Fixed the in-place spiller and trivial rewriter, which had been broken by the recent SlotIndexes work.

llvm-svn: 89238

Added getSubRegIndex(A,B) that returns subreg index of A to B. Use it to replace broken code in VirtRegRewriter.

llvm-svn: 88753

- If destination is a physical register and it has a subreg index, use the
  sub-register instead.
This fixes PR5423.

llvm-svn: 88745

llvm-svn: 88738

llvm-svn: 88719

Set the ReloadReuse AsmPrinter flag where appropriate.

llvm-svn: 87030

the second (store) instruction in SpillSlotToUsesMap
consistently.  I don't think this matters functionally,
but it's cleaner and Evan wants it this way.

llvm-svn: 85463

to spill after all, we weren't handling 2-instruction
spill sequences correctly (PPC Altivec).  We need to
remove the store in this case.  Removing the other
instruction(s) would be goodness but is not needed for
correctness, and isn't done here.  7331562.

llvm-svn: 85437

  bootstrapping. It's not safe to leave identity subreg_to_reg and insert_subreg
  around.
- Relax register scavenging to allow use of partially "not-live" registers. It's
  common for targets to operate on registers where the top bits are undef. e.g.
  s0 =
  d0 = insert_subreg d0<undef>, s0, 1
  ...
     = d0
  When the insert_subreg is eliminated by the coalescer, the scavenger used to
  complain. The previous fix was to keep to insert_subreg around. But that's
  brittle and it's overly conservative when we want to use the scavenger to 
  allocate registers. It's actually legal and desirable for other instructions
  to use the "undef" part of d0. e.g.
  s0 =
  d0 = insert_subreg d0<undef>, s0, 1
  ...
  s1 =
     = s1
     = d0
  We probably need add a "partial-undef" marker on machine operand so the
  machine verifier would not complain.

llvm-svn: 85091

llvm-svn: 85047

VISIBILITY_HIDDEN removal.

llvm-svn: 85043

Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.

llvm-svn: 85042

bootstrap of FSF-style PPC, so there is some
reason to believe the original bug (which was
never analyzed) has been fixed, probably by
82266.

llvm-svn: 83871

icc (#177, partial).  Patch by Erick Tryzelaar.

llvm-svn: 81106

Fixed a test that ensures the LocalRewriter does not attempt to
avoid reloads by reusing clobbered registers.

This was causing issues in 256.bzip2 when compiled with PIC for
a while (starting at r78217), though the problem has since been masked. 

llvm-svn: 80872

When undoing a reuse in ReuseInfo::GetRegForReload, check if it was only a
sub-register being used. The MachineOperand::getSubReg() method is only valid
for virtual registers, so we have to recover the sub-register index manually.

llvm-svn: 79855

llvm-svn: 79852

llvm-svn: 79812

In the included test case, a stack load was not included in DistanceMap. That
caused TransferDeadness to ignore the instruction, leading to a scavenger
assert.

llvm-svn: 79090

llvm-svn: 78363

Add reload and remat backscheduling.  This is disabled by default.  Use
-schedule-spills=true to enable.

llvm-svn: 77327

 - Some clients which used DOUT have moved to DEBUG. We are deprecating the
   "magic" DOUT behavior which avoided calling printing functions when the
   statement was disabled. In addition to being unnecessary magic, it had the
   downside of leaving code in -Asserts builds, and of hiding potentially
   unnecessary computations.

llvm-svn: 77019

Let each target determines whether a machine instruction is dead. If true, that allows late codeine passes to delete it.

This is considered a workaround. The problem is some targets are not modeling side effects correctly. PPC is apparently one of those. This patch allows ppc llvm-gcc to bootstrap on Darwin. Once we find out which instruction definitions are wrong, we can remove the PPCInstrInfo workaround.

llvm-svn: 76703

Another rewriter bug exposed by recent coalescer changes. ReuseInfo::GetRegForReload() should make sure the "switched" register is in the desired register class. I'm surprised this hasn't caused more failures in the past.

llvm-svn: 76558