- Jan 10, 2014
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Venkatraman Govindaraju authored
[Sparc] Add support for parsing jmpl instruction and make indirect call and jmp instructions as aliases to jmpl. llvm-svn: 198909
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Kevin Enderby authored
branch to the next instruction. This can not be encoded but can be turned into a NOP. rdar://15062072 llvm-svn: 198904
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- Jan 08, 2014
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Ana Pazos authored
llvm-svn: 198791
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Roman Divacky authored
resolution works. llvm-svn: 198780
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David Woodhouse authored
llvm-svn: 198763
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David Woodhouse authored
They do *different* things to %esp, so they are not equivalent. Rename PUSHi8 to PUSH32i8 and add the missing PUSH16i8. llvm-svn: 198761
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David Woodhouse authored
We can't do a perfect job here. We *have* to allow (%dx) even in 64-bit mode, for example, because it might be used for an unofficial form of the in/out instructions. We actually want to do a better job of validation *later*. Perhaps *instead* of doing it where we are at the moment. But for now, doing what validation we *can* do in the place that the code already has its validation, is an improvement. llvm-svn: 198760
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David Woodhouse authored
It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? llvm-svn: 198759
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David Woodhouse authored
Where "where possible" means that it's an immediate value and it's below 0x10000. In fact GAS will either truncate or error with larger values, and will insist on using the addr32 prefix to get 32-bit addressing. So perhaps we should do that, in a later patch. llvm-svn: 198758
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David Woodhouse authored
JCXZ should have the 0x67 prefix only if we're in 32-bit mode, so make that appropriately conditional. And JECXZ needs the prefix instead. llvm-svn: 198757
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David Woodhouse authored
I couldn't see how to do this sanely without splitting RETQ from RETL. Eric says: "sad about the inability to roundtrip them now, but...". I have no idea what that means, but perhaps it wants preserving in the commit comment. llvm-svn: 198756
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David Woodhouse authored
llvm-svn: 198755
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David Woodhouse authored
llvm-svn: 198754
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David Woodhouse authored
llvm-svn: 198753
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David Woodhouse authored
This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
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Venkatraman Govindaraju authored
llvm-svn: 198740
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Venkatraman Govindaraju authored
llvm-svn: 198738
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Saleem Abdulrasool authored
Operands which involved label arithemetic would previously fail to parse. This corrects that by adding the additional case for the shift operand validation. llvm-svn: 198735
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- Jan 07, 2014
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Roman Divacky authored
take type from the new symbol but merge them so that the type is never "downgraded". This is probably quite rare, except for IFUNC symbols which we used to misassemble, losing the IFUNC type. Fixes #18372. llvm-svn: 198706
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David Peixotto authored
This commit adds the pre-UAL aliases of fconsts and fconstd for vmov.f32 and vmov.f64. They use an InstAlias rather than a MnemonicAlias to properly support the predicate operand. We need to support encoded 8-bit constants in order to implement the pre-UAL fconsts/fconstd aliases for vmov.f32/vmov.f64, so this commit also fixes parsing of encoded floating point constants used in vmov.f32/vmov.f64 instructions. Now we can support assembly code like this: fconsts s0, #0x70 which is equivalent to vmov.f32 s0, #1.0. Most of the code was already in place to support this feature. Previously the code was trying to accept encoded 8-bit float constants for the vmov.f32/vmov.f64 instructions. It looks like the support for parsing encoded floats was lost in a refactoring in commit r148556 and we did not have any tests in place to catch it. The change in this commit is to keep the parsed value as a 32-bit float instead of a 64-bit double because that is what the isFPImm() function expects to find. There is no loss of precision by using a 32-bit float here because we are still limited to an 8-bit encoded value in the end. Additionally, we explicitly reject encoded 8-bit floats for vmovf.32/64. This is the same as the current behavior, but we now do it explicitly rather than accidently. llvm-svn: 198697
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Venkatraman Govindaraju authored
Also, correct the offsets for FixupsKindInfo. llvm-svn: 198681
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Saleem Abdulrasool authored
Switch the context to be SmallVectors. This allows for saving additional context when providing previous emission sites. llvm-svn: 198665
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Saleem Abdulrasool authored
Move the unwinding context for the ARM IAS into a helper class. This is purely a structural refactoring. A follow up change allows for recording additional depth to improve diagnostics. llvm-svn: 198664
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Saleem Abdulrasool authored
Parse tag names as well as expressions. The former is part of the specification, the latter is for improved compatibility with the GNU assembler. Fix attribute value handling to be comformant to the specification. llvm-svn: 198662
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Saleem Abdulrasool authored
Introduce a new virtual method Note into the AsmParser. This completements the existing Warning and Error methods. Use the new method to clean up the output of the unwind routines in the ARM AsmParser. llvm-svn: 198661
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Venkatraman Govindaraju authored
llvm-svn: 198658
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Jack Carter authored
This patch adds .abicalls and .set pic0 support which affects the ELF ABI and its flags. In addition the patch uses a common interface for both the MipsTargetSteamer and MipsObjectStreamer that both the integrated and standalone assemblers will use for the output for these directives. llvm-svn: 198646
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- Jan 06, 2014
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Venkatraman Govindaraju authored
llvm-svn: 198591
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Craig Topper authored
The 0x66 prefix toggles between 16-bit and 32-bit addressing mode. So in 32-bit mode it is used to switch to 16-bit addressing mode for the following instruction, while in 16-bit mode it's the other way round — it's used to switch to 32-bit mode instead. Thus, emit the 0x66 prefix byte for OpSize only in 32-bit (and 64-bit) mode, and introduce a new OpSize16 bit which is used in 16-bit mode instead. This is just the basic infrastructure for that change; a subsequent patch will add the new OpSize16 bit to the 32-bit instructions that need it. Patch from David Woodhouse. llvm-svn: 198586
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Craig Topper authored
This is not really expected to work right yet. Mostly because we will still emit the OpSize (0x66) prefix in all the wrong places, along with a number of other corner cases. Those will all be fixed in the subsequent commits. Patch from David Woodhouse. llvm-svn: 198584
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- Jan 05, 2014
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Craig Topper authored
Add some tests to validate correct register selection, including a fix to an existing test which was requiring the *wrong* output. Patch from David Woodhouse. llvm-svn: 198566
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Venkatraman Govindaraju authored
llvm-svn: 198536
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Venkatraman Govindaraju authored
llvm-svn: 198533
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Craig Topper authored
Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test. llvm-svn: 198530
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- Jan 03, 2014
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Ana Pazos authored
llvm-svn: 198437
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- Jan 02, 2014
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Logan Chien authored
llvm-svn: 198313
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- Jan 01, 2014
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Craig Topper authored
Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits. llvm-svn: 198278
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Craig Topper authored
llvm-svn: 198269
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- Dec 31, 2013
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Craig Topper authored
llvm-svn: 198268
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Craig Topper authored
Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases. llvm-svn: 198265
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