llvm-svn: 40123

InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033

llvm-svn: 40030

llvm-svn: 39962

This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.

After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be 
thought as 'finished': I expect many small and not so small glitches
everywhere.

llvm-svn: 39855

following jump tables that it earlier inserted.  This
would be OK on other targets but is needed for correctness
only on ARM (constant islands needs to find jump tables).

llvm-svn: 39782

of size other than 4).

llvm-svn: 39743

llvm-svn: 38515

llvm-svn: 38513

llvm-svn: 38501

zero if they see a target triple they don't understand.

llvm-svn: 38463

llvm-svn: 37965

llvm-svn: 37962

llvm-svn: 37961

llvm-svn: 37932

llvm-svn: 37931

llvm-svn: 37926

llvm-svn: 37914

Almost all occurrences of "bytecode" in the sources have been eliminated.

llvm-svn: 37913

llvm-svn: 37898

llvm-svn: 37897

llvm-svn: 37896

Each ARM use predicate operand is now made up of two components. The new component is the CPSR register.

llvm-svn: 37895

llvm-svn: 37894

llvm-svn: 37801

llvm-svn: 37737

instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728

llvm-svn: 37705

TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.

llvm-svn: 37704

llvm-svn: 37700

llvm-svn: 37669

llvm-svn: 37659

with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644

llvm-svn: 37643

llvm-svn: 37606

llvm-svn: 37571

llvm-svn: 37528

llvm-svn: 37527

llvm-svn: 37517

llvm-svn: 37516