InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033

llvm-svn: 38501

llvm-svn: 37965

llvm-svn: 37961

llvm-svn: 37931

llvm-svn: 37914

Each ARM use predicate operand is now made up of two components. The new component is the CPSR register.

llvm-svn: 37895

instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728

llvm-svn: 37705

llvm-svn: 37659

with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644

llvm-svn: 37643

llvm-svn: 37468

llvm-svn: 37388

llvm-svn: 37381

llvm-svn: 37349

llvm-svn: 37271

llvm-svn: 37269

Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code.

llvm-svn: 37199

Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable.

llvm-svn: 37118

llvm-svn: 37103

llvm-svn: 37066

llvm-svn: 36948

llvm-svn: 36519

llvm-svn: 36518

llvm-svn: 36506

llvm-svn: 36222

flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).

llvm-svn: 35573

llvm-svn: 35381

    mov lr, pc
    bx lr
So, the function was not called.

llvm-svn: 35218

Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool.

llvm-svn: 35207

llvm-svn: 35163

rematerializable. Only used for constant generation for now.

llvm-svn: 35162

llvm-svn: 35161

llvm-svn: 33832

        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

- In thumb mode, it's not possible to use .set generate a pc relative stub
  address. The stub is ARM code which is in a different section from the thumb
  code. Load the value from a constpool instead.
- Some asm printing clean up.

llvm-svn: 33664

llvm-svn: 33537

llvm-svn: 33368

llvm-svn: 33353

patch by Lauro
bug fixed by me

llvm-svn: 32795