Commits · 2fc851002b34f6b30e947f82611f4331cd38c93d · Roger Ferrer / llvm-epi-0.8 · GitLab

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Sep 18, 2014
- [FastISel][AArch64] Followup commit for 218031 to handle negative offsets too. · 2fc85100
  Juergen Ributzka authored Sep 18, 2014
  2fc85100
- [FastISel][AArch64] Try to fold the offset into the add instruction when... · a33070c3
  Juergen Ributzka authored Sep 18, 2014
  a33070c3
- [FastISel][AArch64] Fold 'AND' instruction during the address computation. · 99b7758b
  Juergen Ributzka authored Sep 18, 2014
  99b7758b
- [FastISel][AArch64] Fold bit test and branch into TBZ and TBNZ. · c35fb036
  Juergen Ributzka authored Sep 18, 2014
  c35fb036
Sep 17, 2014
- [FastISel][AArch64] Custom lower sdiv by power-of-2. · f6430314
  Juergen Ributzka authored Sep 17, 2014
  f6430314
- [FastISel][AArch64] Simplify mul to shift when possible. · c611d727
  Juergen Ributzka authored Sep 17, 2014
  c611d727
- [FastISel][AArch64] Fold mul into add/sub and logical operations. · 3871c694
  Juergen Ributzka authored Sep 17, 2014
  3871c694
- [FastISel][AArch64] Fold mul into the address computation of memory operations. · 22d4cd0a
  Juergen Ributzka authored Sep 17, 2014
  22d4cd0a
- [FastISel][AArch64] Fold compare with zero and branch into CBZ and CBNZ. · d8e30c0d
  Juergen Ributzka authored Sep 17, 2014
  d8e30c0d
- [FastISel][AArch64] Improve branch selection to support all FP conditions. · fb3e1437
  Juergen Ributzka authored Sep 17, 2014
  fb3e1437
Sep 16, 2014
- [FastISel][AArch64] Add vector support to argument lowering. · 59e631c7
  Juergen Ributzka authored Sep 16, 2014
  59e631c7
- [FastISel][AArch64] Add missing test case for previous commit. · f693787e
  Juergen Ributzka authored Sep 15, 2014
  f693787e
- [FastISel][AArch64] Lower sin/cos/pow to runtime lib calls. · 993224a5
  Juergen Ributzka authored Sep 15, 2014
  993224a5
- [FastISel][AArch64] Add lowering support for frem. · afa034fb
  Juergen Ributzka authored Sep 15, 2014
  afa034fb
Sep 15, 2014
- [FastISel][AArch64] Improve floating-point compare support. · 8984f48d
  Juergen Ributzka authored Sep 15, 2014
  8984f48d
Sep 14, 2014
- [FastISel][AArch64] Add support for non-native types for logical ops. · 85c1f846
  Juergen Ributzka authored Sep 13, 2014
  85c1f846
Sep 12, 2014
- [AArch64] Enable post-RA MI scheduler. · 486e087f
  Chad Rosier authored Sep 12, 2014
  486e087f
Sep 11, 2014
- Add DAG combine for shl + add of constants. · 8239eaab
  Matt Arsenault authored Sep 11, 2014
  8239eaab
- [AArch64] Reenable the PBQP test now that the leak issue has been fixed. · 36902667
  Arnaud A. de Grandmaison authored Sep 11, 2014
  36902667
- Build correct vector filled with undef nodes · f7aff68f
  David Xu authored Sep 11, 2014
  f7aff68f
Sep 10, 2014
- [AArch64] Temporarily desactivate the PBQP test, while I investigate some leaks in the allocator · d17f96c9
  Arnaud A. de Grandmaison authored Sep 10, 2014
  d17f96c9
- [AArch64] Add experimental PBQP support · c75dbbbd
  Arnaud A. de Grandmaison authored Sep 10, 2014
  c75dbbbd
- [AArch 64] Use a constant pool load for weak symbol references when · 369c0306
  Asiri Rathnayake authored Sep 10, 2014
  369c0306
Sep 08, 2014
- [AArch64] Improve AA to remove unneeded edges in the AA MI scheduling graph. · 3528c1e4
  Chad Rosier authored Sep 08, 2014
  3528c1e4
Sep 05, 2014
- [AArch64] Add pass to enable additional comparison optimizations by CSE. · 1a486da5
  Jiangning Liu authored Sep 05, 2014
  1a486da5
Sep 04, 2014
- AArch64: fix vector-immediate BIC/ORR on big-endian devices. · f7423fd0
  Tim Northover authored Sep 04, 2014
  f7423fd0
- AArch64: fix big-endian immediate materialisation · bb72e6c8
  Tim Northover authored Sep 04, 2014
  bb72e6c8
- Revert r216803 "[MachineSinking] Clear kill flag of all operands at all their uses." · 4bea4945
  Juergen Ributzka authored Sep 04, 2014
  4bea4945
- [FastISel][AArch64] Add target-specific lowering for logical operations. · 1dbc15f0
  Juergen Ributzka authored Sep 04, 2014
  1dbc15f0
Sep 03, 2014
- Reapply r216805 "[MachineCombiner][AArch64] Use the correct register class for MADD, SUB, and OR."" · 31e5b7fb
  Juergen Ributzka authored Sep 03, 2014
  31e5b7fb
- [FastISel][AArch64] Add target-dependent instruction selection for Add/Sub. · a1148b21
  Juergen Ributzka authored Sep 03, 2014
  a1148b21
- [FastISel][AArch64] Use the target-dependent selection code for shifts first. · 53dbef6e
  Juergen Ributzka authored Sep 02, 2014
  53dbef6e
Sep 02, 2014
- Replace -use-init-array with -use-ctors. · 4dd3677b
  Rafael Espindola authored Sep 02, 2014
  4dd3677b
- Merge Extend and Shift into a UBFX · 052b9d92
  David Xu authored Sep 02, 2014
  052b9d92
- Revert "Revert '[DAGCombiner] Split up an indexed load if only the base pointer value is live'" · 51e6fa22
  Hal Finkel authored Sep 02, 2014
  51e6fa22
Sep 01, 2014
- [MachineSink] Use the real post dominator tree · 5208cc5d
  Jingyue Wu authored Sep 01, 2014
  5208cc5d
Aug 30, 2014
- Revert r216805 "[MachineCombiner][AArch64] Use the correct register class for MADD, SUB, and OR." · 25816b0f
  Juergen Ributzka authored Aug 30, 2014
  25816b0f
- [MachineCombiner][AArch64] Use the correct register class for MADD, SUB, and OR. · 3e7f88c1
  Juergen Ributzka authored Aug 29, 2014
  3e7f88c1
- [FastISel][AArch64] Use the correct register class for branches. · c5c1c609
  Juergen Ributzka authored Aug 29, 2014
  c5c1c609
- [MachineSinking] Clear kill flag of all operands at all their uses. · 00d78221
  Juergen Ributzka authored Aug 29, 2014
  00d78221