1. Sinking would crash when the first instruction of a block was
   sunk due to iterator problems.
2. Instructions could be sunk to their current block, causing an
   infinite loop.

This fixes PR3968

llvm-svn: 68787

llvm-svn: 68786

llvm-svn: 68783

With this we generate

movl    %gs:0, %eax
leal    i@NTPOFF(%eax), %eax

instead of

movl    $i@NTPOFF, %eax
addl    %gs:0, %eax

llvm-svn: 68778

llvm::PointerType::get().  Patch by Anders Johnsen!

llvm-svn: 68772

It turns out that there are still several problems with this, will file a bugzilla.

llvm-svn: 68749

llvm-svn: 68747

llvm-svn: 68745

code that uses it by using SelectionDAG::getVTList instead.

llvm-svn: 68744

the key. This will cause it to create a new std::string, which isn't
wanted. Instead, pass back the "const char*". Modify the EmitString() method to
take a "const char*".

llvm-svn: 68741

llvm-svn: 68735

isRegTiedToDefOperand.  Thanks to Bob for pointing this out!

llvm-svn: 68734

llvm-svn: 68730

gives a micro speedup in the Dwarf writer.

llvm-svn: 68728

llvm-svn: 68727

register destinations that are tied to source operands.  The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly.  The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).

llvm-svn: 68714

The way we are trying to figure out banksel immediate operand may yield different results for different type of insns. This will eventually need to be changed but currently let us prevent the crash in cases of incorrect detection of banksel operand.

llvm-svn: 68713

attached testcase.

llvm-svn: 68712

Arguments to indirect calls were being passed incorrectly. They are not fixed to start after return value.

llvm-svn: 68705

llvm-svn: 68690

r68576 unconverd a bug in PIC16 port (Thanks to Dan Gohman) where we were custom lowering an ADD to ADDC.

llvm-svn: 68671

in addition to ZERO_EXTEND and SIGN_EXTEND. Fix a bug in the
way it checked for live-out values, and simplify the way it
find users by using SDNode::use_iterator's (relatively) new
features. Also, make it slightly more permissive on targets
with free truncates.

In SelectionDAGBuild, avoid creating ANY_EXTEND nodes that are
larger than necessary. If the target's SwitchAmountTy has
enough bits, use it. This exposes the truncate to optimization
early, enabling more optimizations.

llvm-svn: 68670

Convert TargetRegisterInfo's super-register checking to use a pre-computed hash table just like subregister checking does.

llvm-svn: 68669

eagerly. This helps avoid CopyToReg nodes in some cases where they
aren't needed, and also helps subsequent optimizer heuristics
in cases where the extra nodes would cause the node to appear
to have multiple results. This doesn't have a significant impact
currently; it'll help an upcoming change.

llvm-svn: 68667

llvm-svn: 68666

llvm-svn: 68663

If subprogram type is not tagged as DW_TAG_subroutine_type then use it directly as a return value type.

llvm-svn: 68647

Tested by bootstrapping llvm-gcc and using that to build llvm.

llvm-svn: 68645

ARMTargetLowering::isLegalAddressingMode.

llvm-svn: 68619

llvm-svn: 68614

llvm-svn: 68607

llvm-svn: 68603

Emit .line debug directives for stoppoints. The debug location is retrieved by the MachineInstr itself, rather than by custom handling the DBG_STOPPOINT nodes.

llvm-svn: 68602

integer types, unless they are already strange.  This prevents it from
turning the code produced by SROA into crazy libcalls and stuff that 
the code generator can't handle.  In the attached example, the result
was an i96 multiply that caused the x86 backend to assert.

Note that if TargetData had an idea of what the legal types are for
a target that this could be used to stop instcombine from introducing
i64 muls, as Scott wanted.

llvm-svn: 68598

Every function has the address of its frame in the beginning of code section.
The frame address is retrieved and used to pass arguments.

llvm-svn: 68597

a testcase I'm about to attach to that pr.

llvm-svn: 68592

abstraction for CommandLine.

llvm-svn: 68588

avoiding sign extension for the top octet.  For "negative" chars, we'd print
stuff like:

.asciz	"\702...
now we print:
.asciz	"\302...

llvm-svn: 68577

with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.

This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.

Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.

Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.

Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.

Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.

llvm-svn: 68576

llvm-svn: 68569