llvm-svn: 119128

Switch the ARM backend to use 'let' instead of 'set' with this change.

llvm-svn: 119120

It can pass two tests below on Win32.
  - Clang :: CodeGenCXX/dyncast.cpp
  - LLVM :: CodeGen/ARM/globals.ll

llvm-svn: 119023

llvm-svn: 118829

Add support for specifying a PostEncoderMethod, which can perform post-processing after the automated encoding of an instruction.
Not yet used.

llvm-svn: 118759

their comments.

llvm-svn: 118696

llvm-svn: 118622

llvm-svn: 118359

fixed physical registers.  Start moving fp comparison
aliases to the .td file (which default to using %st1 if
nothing is specified).

llvm-svn: 118352

add fixed immediate values.  Move the aad and aam aliases to
use this, and document it.

llvm-svn: 118350

result instruction operand numbering matched the result pattern.

Fixing this allows us to move the xchg/test aliases to the .td file.

llvm-svn: 118334

from c++ hacks to proper .td InstAlias definitions.  Change them!

llvm-svn: 118330

operand list instead of the operand list redundantly declared on the alias
or instruction.

With this change, we finally remove the ins/outs list on the alias.  Before:
  def : InstAlias<(outs GR16:$dst), (ins GR8 :$src),
                  "movsx $src, $dst",
                  (MOVSX16rr8W GR16:$dst, GR8:$src)>;
After:
  def : InstAlias<"movsx $src, $dst",
                  (MOVSX16rr8W GR16:$dst, GR8:$src)>;

This also makes the alias mechanism more general and powerful, which will
be exploited in subsequent patches.

llvm-svn: 118329

  (someinst GR16:$foo, GR32:$foo)

Reimplement BuildAliasOperandReference to be correctly
based on the names of operands in the result pattern,
instead of on the instruction operand definitions.

llvm-svn: 118328

llvm-svn: 118327

llvm-svn: 118326

llvm-svn: 118325

file instead of the asmmatcher.

llvm-svn: 118324

and as such can be represented by an MVT - the more complicated
EVT is not needed.  Use MVT for ValVT everywhere.

llvm-svn: 118245

Right now the code is partitioned but the behavior is the same.
This should be improved in the near future.   This removes some
uses of TheOperandList.

llvm-svn: 118232

it doesn't do any lexical stuff anymore.

llvm-svn: 118230

llvm-svn: 118228

on the incoming operand list.  This also makes the code simpler.

llvm-svn: 118225

llvm-svn: 118219

now matchables contain an explicit list of how to populate each
operand in the result instruction instead of having them somehow
magically be correlated to the input inst.

llvm-svn: 118217

Fixups list for the instruction so the operand encoders can add to it as
needed.

llvm-svn: 118206

llvm-svn: 118190

value type, so there is no point in passing it around using
an EVT.  Use the simpler MVT everywhere.  Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.

llvm-svn: 118167

parts. Represent the operation mode as an optional operand instead.
rdar://8614429

llvm-svn: 118137

ins/outs list that isn't specified by their asmstring.  Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right.  Mark a bunch of ARM instructions that use this as 
isCodeGenOnly.  Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).

llvm-svn: 118119

that have complicated tying going on.

llvm-svn: 118112

filling them in one at a time.  Previously this iterated over the
asmoperands, which left the problem of "holes".  The new approach
simplifies things.

llvm-svn: 118104

in the generated .inc files.

llvm-svn: 118083

llvm-svn: 118031

assumptions about stack layout. Specifically, LR must be saved next to FP.

llvm-svn: 118026

llvm-svn: 118025

merging it into a Token field in Operand, and moving the first
token to an explicit mnemonic field.  These were parallel
arrays before (except for the mnemonic) which kept confusing me.

llvm-svn: 118024

llvm-svn: 117993

llvm-svn: 117987

FWIW, X86 has 254 ambiguous instructions.

llvm-svn: 117979