scavenger gets confused about register liveness if it doesn't see them.
I'm not thrilled with this solution, but it only comes up when there are dead
copies in the code, which is something that hopefully doesn't happen much.

Here is what happens in pr4100: As shown in the following excerpt from the
debug output of llc, the source of a move gets reloaded from the stack,
inserting a new load instruction before the move.  Since that source operand
is a kill, the physical register is free to be reused for the destination
of the move.  The move ends up being a no-op, copying R3 to R3, so it is
deleted.  But, it leaves behind the load to reload %reg1028 into R3, and
that load is not updated to show that it's destination operand (R3) is dead.
The scavenger gets confused by that load because it thinks that R3 is live.

Starting RegAlloc of: %reg1025<def,dead> = MOVr %reg1028<kill>, 14, %reg0, %reg0
  Regs have values: 
  Reloading %reg1028 into R3
  Last use of R3[%reg1028], removing it from live set
  Assigning R3 to %reg1025
  Register R3 [%reg1025] is never used, removing it from live set

Alternative solutions might be either marking the load as dead, or zapping
the load along with the no-op copy.  I couldn't see an easy way to do
either of those, though.

llvm-svn: 71196

llvm-svn: 71180

llvm-svn: 71179

register destinations that are tied to source operands.  The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly.  The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).

llvm-svn: 68714

llvm-svn: 67335

Local register allocator shouldn't assume only the entry and landing pad basic blocks have live-ins.

llvm-svn: 63323

llvm-svn: 63267

A slight compile time optimization. If the caller knows there isn't a free register getReg() should not call getFreeReg().

llvm-svn: 63263

llvm-svn: 62600

llvm-svn: 60586

llvm-svn: 59961

instead of requiring all "short description" strings to begin with
two spaces. This makes these strings less mysterious, and it fixes
some cases where short description strings mistakenly did not
begin with two spaces.

llvm-svn: 57521

Fix the case where an instruction is not properly marked as using all registers that alias its inputs.

llvm-svn: 57286

was setting kill flags on tied uses in two-address instructions.
The kill flags were causing the allocator to think it could
allocate the use and its tied def in different registers.

llvm-svn: 57039

isReg, etc., from isRegister, etc.

llvm-svn: 57006

for earlyclobbers.  Teach Local RA about earlyclobber,
and add some tests for it.

llvm-svn: 56592

isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.

llvm-svn: 56189

llvm-svn: 55779

Patch contributed by m-s.

llvm-svn: 55167

llvm-svn: 53414

- Change the horrible N^2 isRegReDefinedByTwoAddr. Now callers must supply the operand index of def machineoperand and at most one full scan of non-implicit operands is needed.
- Change local register allocator to use the new isRegReDefinedByTwoAddr instead of reinventing the wheel.

llvm-svn: 53394

Use DenseMap instead of std::map in local register allocation.  This improves the time on instcombine from .31s to .22s

llvm-svn: 53390

llvm-svn: 53389

llvm-svn: 53378

Loosen our check here.  Local regalloc only cares that the reg is used and def'd by the same instruction, but about the details of
the relationship.

llvm-svn: 53367

Don't use an expensive check for two-address-ness when we have the information sitting around to determine it much more quickly,
This speeds up the local register allocator from 0.37s to 0.31s on instcombine.

llvm-svn: 53359

llvm-svn: 53352

Keep RegAllocSimple in sync.

llvm-svn: 53351

of having local variables duplicate it.

llvm-svn: 53346

with extra checks.

llvm-svn: 53344

Fix the build.  Apparently MachineInstr& is no longer implicitly convertable to MachineBasicBlock::iterator.

llvm-svn: 53260

rather than depending on LiveVariables.  This decreases compile time from:
0.5909s (LV + Regalloc) to 0.421s (just regalloc).

llvm-svn: 53256

llvm-svn: 51647

several things that were neither in an anonymous namespace nor static
but not intended to be global.

llvm-svn: 51017

llvm-svn: 49099

findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies.

llvm-svn: 47927

that instruction as its "last use". This fixes PR1925.

llvm-svn: 47758

llvm-svn: 47629

would have been a Godsend here!

llvm-svn: 47625

Really really bad local register allocator bug. On X86, it was never using ESI, EDI, and EBP because of a bug in RALocal::isPhysRegAvailable(). For example, when
it checks if ESI is available, it then looks at registers aliases to ESI. SIL is marked -2 (not allocatable) but isPhysRegAvailable() incorrectly assumes it is in use and returns false for ESI.

llvm-svn: 47499