Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.

llvm-svn: 138795

llvm-svn: 138771

Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.

llvm-svn: 138675

invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons.  We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts.  Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits.  This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.

llvm-svn: 138653

Support an extension of ARM asm syntax to allow immediate operands to ADR instructions.  This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.

llvm-svn: 138635

llvm-svn: 138626

llvm-svn: 138623

Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.

llvm-svn: 138575

Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.

llvm-svn: 138552

Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.

llvm-svn: 138551

llvm-svn: 138441

Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.

llvm-svn: 138341

Fix two more instances of mis-matched operand names breaking disassembly.  Found by randomized testing.

llvm-svn: 138337

llvm-svn: 138336

llvm-svn: 138301

llvm-svn: 138300

llvm-svn: 138298

llvm-svn: 138292

Provide operand encoding information for half-precision VCVT instructions.  Found by randomized testing.

llvm-svn: 138273

Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.

llvm-svn: 138269

llvm-svn: 138255

llvm-svn: 138251

llvm-svn: 138250

llvm-svn: 138246

llvm-svn: 138034

STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
Found by randomized testing.

llvm-svn: 138003

llvm-svn: 138000

Fixes a large class of disassembler crashes found by randomized testing.

llvm-svn: 137995

Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.

llvm-svn: 137986

llvm-svn: 137974

Test commit; adding test for invalid LDRD which was part of the patch for r137647 but seemingly didn't get svn add'ed.

llvm-svn: 137960

llvm-svn: 137954

llvm-svn: 137902

llvm-svn: 137840

Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid.  Only used for ARM UNPREDICTABLE instructions at the moment.
Patch by James Molloy.

llvm-svn: 137830

llvm-svn: 137687

llvm-svn: 137657

Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode.  Update tests to reflect this fact.
Patch by James Molloy.

llvm-svn: 137647

llvm-svn: 137645

llvm-svn: 137644