Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.

llvm-svn: 138795

llvm-svn: 138771

llvm-svn: 138623

Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.

llvm-svn: 138552

Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.

llvm-svn: 138551

llvm-svn: 138034

Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32.  This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb.  Part of PR8873.

llvm-svn: 135337

VEX prefixes are working for triadic AVX
instructions.  This concludes the patch set to
enable AVX support for the X86 disassebler.

llvm-svn: 127647

it to ignore valid uses of FS and GS as additional
base registers in address computations.  Added a test
case for this.

llvm-svn: 126302

fixed in r126147, where a field in the X86 decode
structure was being read as bits, not bytes.

llvm-svn: 126182

Patch by Richard Simth.

llvm-svn: 122962

llvm-svn: 119050