llvm-svn: 48137

Avoid creating BUILD_VECTOR of all zero elements of "non-normalized" type (e.g. v8i16 on x86) after legalizer. Instruction selection does not expect to see them. In all likelihood this can only be an issue in a bugpoint reduced test case.

llvm-svn: 48136

llvm-svn: 48135

the build system.  Patch by Joachim Durchholz  for PR2121

llvm-svn: 48134

llvm-svn: 48133

before compile_c.  Patch by Joachim Durchholz!

llvm-svn: 48132

llvm-svn: 48123

llvm-svn: 48121

llvm-svn: 48116

llvm-svn: 48110

an RFP register class.

Teach ScheduleDAG how to handle CopyToReg with different src/dst 
reg classes.

This allows us to compile trivial inline asms that expect stuff
on the top of x87-fp stack.

llvm-svn: 48107

in different register classes, e.g. copy of ST(0) to RFP*.  This gets
some really trivial inline asm working that plops things on the top of
stack (PR879)

llvm-svn: 48105

llvm-svn: 48103

Secondly, we have to check whether the branch is actually pointing to the block
with the unwind in it. We could have gotten here because of the unwind_to alone.

llvm-svn: 48099

at all.

llvm-svn: 48096

llvm-svn: 48092

into a vector of zeros or undef, and when the top part is obviously
zero, we can just use movd + shuffle.  This allows us to compile
vec_set-B.ll into:

_test3:
	movl	$1234567, %eax
	andl	4(%esp), %eax
	movd	%eax, %xmm0
	ret

instead of:

_test3:
	subl	$28, %esp
	movl	$1234567, %eax
	andl	32(%esp), %eax
	movl	%eax, (%esp)
	movl	$0, 4(%esp)
	movq	(%esp), %xmm0
	addl	$28, %esp
	ret

llvm-svn: 48090

llvm-svn: 48086

removal of invoke, PR1269.

llvm-svn: 48084

#include <xmmintrin.h>
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}

into:
	movl	$1, %eax
	movd	%eax, %xmm0
	ret

instead of a constant pool load.

llvm-svn: 48063

llvm-svn: 48062

llvm-svn: 48061

_test3:
	movd	%rdi, %xmm1
	#IMPLICIT_DEF %xmm0
	punpcklqdq	%xmm1, %xmm0
	ret

instead of:

_test3:
	#IMPLICIT_DEF %rax
	movd	%rax, %xmm0
	movd	%rdi, %xmm1
	punpcklqdq	%xmm1, %xmm0
	ret

This is still not ideal.  There is no reason to two xmm regs.

llvm-svn: 48058

llvm-svn: 48045

Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.

llvm-svn: 48042

llvm-svn: 48041

llvm-svn: 48033

llvm-svn: 48029

Fixed a register scavenger bug. If a def is re-defining part of a super register, there must be an implicit def of the super-register on the MI.

llvm-svn: 48024

llvm-svn: 48020

llvm-svn: 48016

we're using SSE or not.  This fixes PR2122.

llvm-svn: 48006

llvm-svn: 48005

llvm-svn: 47996

llvm-svn: 47992

llvm-svn: 47990

llvm-svn: 47988

under modulo (overflow). Fixes PR1933.

llvm-svn: 47987

upper and lower 32-bits are the same (in addition to 0 and -1 previously.)

llvm-svn: 47985

- select_bits.ll now fully functional now that PR1993 is closed. It was
  previously broken by refactoring in SPUInstrInfo.td and using multiclasses.
- Same for eqv.ll

llvm-svn: 47972