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  1. Jan 11, 2010
    • Evan Cheng's avatar
      Select an OR with immediate as an ADD if the input bits are known zero. This... · 64d9f405
      Evan Cheng authored
      Select an OR with immediate as an ADD if the input bits are known zero. This allow the instruction to be 3address-fied if needed.
      
      llvm-svn: 93152
      64d9f405
    • David Greene's avatar
      · 206351a1
      David Greene authored
      Implement a feature (-vector-unaligned-mem) to allow targets to
      ignore alignment requirements for SIMD memory operands.  This
      is useful on architectures like the AMD 10h that do not trap on
      unaligned references if a status bit is twiddled at startup time.
      
      llvm-svn: 93151
      206351a1
  2. Jan 09, 2010
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