llvm-svn: 168337

the zero GV check inside, so we won't forget it at the caller side.

llvm-svn: 168328

It turned out that ARM wants different layout of type infos.
This is yet another patch in attempt to fix PR7187 

llvm-svn: 168325

depending on them being emitted before the text and/or data
sections and testing didn't uncover any.

llvm-svn: 168321

PR14376.

llvm-svn: 168320

llvm-svn: 168294

On PPC the stack pointer is X1, but ADJCALLSTACK writes R1.

Fixes PR14315: Register regmask dependency problem with misched.

llvm-svn: 168248

llvm-svn: 168240

llvm-svn: 168203

llvm-svn: 168191

llvm-svn: 168183

llvm-svn: 168143

case to vector legalization so this actually works.

Patch by Pete Couperus.  Fixes PR12540.

llvm-svn: 168107

to guarantee deterministic code generation.

llvm-svn: 168074

positive.

In this particular case, R6 was being spilled by the register scavenger when it
was in fact dead.  The isUsed function reported R6 as used because the R6_R7
alias was reserved (due to the fact that we've reserved R7 as the FP).  The
solution is to only check if the original register (i.e., R6) isReserved and
not the aliases.  The aliases are only checked to make sure they're available.

The test case is derived from one of the nightly tester benchmarks and is rather
intractable and difficult to reproduce, so I haven't included it.
rdar://12592448

llvm-svn: 168054

Similarly to several recent fixes throughout the code replace std::map use with the MapVector.
Add find() method to the MapVector.

llvm-svn: 168051

llvm-svn: 168025

Jakub Staszak spotted this in review. I don't notice these things
until I manually rerun benchmarks. But reducing unit tests is a very
high priority.

llvm-svn: 168021

llvm-svn: 167991

llvm-svn: 167972

llvm-svn: 167970

eh table and handler data if there are no landing pads in the function.
Patch by Logan Chien with some cleanups from me.

llvm-svn: 167945

llvm-svn: 167913

llvm-svn: 167912

Do some cleanup of the code while here.

Inspired by patch by Logan Chien!

llvm-svn: 167904

temporarily as it is breaking the gdb bots.

This reverts commit r167806/e7ff4c14b157746b3e0228d2dce9f70712d1c126.

llvm-svn: 167886

llvm-svn: 167880

This option will eventually either be enabled unconditionally or
replaced by a more general live range splitting optimization.

llvm-svn: 167879

llvm-svn: 167877

physical register as candidate for common subexpression elimination
in MachineCSE.

This fixes a bug on PowerPC in MultiSource/Applications/oggenc/oggenc
caused by MachineCSE invalidly merging two separate DYNALLOC insns.

llvm-svn: 167855

Working on reducing unit tests.
This won't be enabled unless a subtarget enables misched.

llvm-svn: 167851

llvm-svn: 167830

This allows me to begin enabling (or backing out) misched by default
for one subtarget at a time. To run misched we typically want to:
- Disable SelectionDAG scheduling (use the source order scheduler)
- Enable more aggressive coalescing (until we decide to always run the coalescer this way)
- Enable MachineScheduler pass itself.

Disabling PostRA sched may follow for some subtargets.

llvm-svn: 167826

This adds the -join-globalcopies option which can be enabled by
default once misched is also enabled.

Ideally, the register coalescer would be able to split local live
ranges in a way that produces copies that can be easily resolved by
the scheduler. Until then, this heuristic should be good enough to at
least allow the scheduler to run after coalescing.

llvm-svn: 167825

For now be more conservative in case other out-of-tree schedulers rely
on the old behavior of artificial edges.

llvm-svn: 167808

If we have a type 'int a[1]' and a type 'int b[0]', the generated DWARF is the
same for both of them because we use the 'upper_bound' attribute. Instead use
the 'count' attrbute, which gives the correct number of elements in the array.
<rdar://problem/12566646>

llvm-svn: 167806

Block priorities still apply outside loops.

llvm-svn: 167793

llvm-svn: 167785

llvm-svn: 167765

This teaches the register coalescer to be less prone to split critical
edges. I am currently benchmarking this with the new (post-coalescer)
scheduler. I plan to enable this by default and remove the option as
soon as misched is enabled.

llvm-svn: 167758