llvm-svn: 109511

llvm-svn: 108556

getMinimalPhysRegClass. It was used to produce spills, and it is better to
use the most specific class if possible.

Update getLoadStoreRegOpcode to handle GR32_AD.

llvm-svn: 108115

The first one was used just to call isSafeToMoveRegClassDefs. In
general, using a more specific reg class is better, in practice only
x86 implements that method and the results are always the same.

The second one is in FindFreeRegister and is used to check if a register
is in a register class, a much more direct call to contains is better as
it should cover more cases and is faster.

llvm-svn: 108093

llvm-svn: 108062

inserted in a MBB, and return an already inserted MI.

This target API change is necessary to allow foldMemoryOperand to call
storeToStackSlot and loadFromStackSlot when folding a COPY to a stack slot
reference in a target independent way.

The foldMemoryOperandImpl hook is going to change in the same way, but I'll wait
until COPY folding is actually implemented. Most targets only fold copies and
won't need to specialize this hook at all.

llvm-svn: 107991

llvm-svn: 107949

EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.

Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.

llvm-svn: 107879

llvm-svn: 106865

is reused as an input.  PR 4118.  Testcase is too big,
as usual with bugs in this area, but there's one in
the PR.

llvm-svn: 106816

instruction defines subregisters.

Any existing subreg indices on the original instruction are preserved or
composed with the new subreg index.

Also substitute multiple operands mentioning the original register by using the
new MachineInstr::substituteRegister() function. This is necessary because there
will soon be <imp-def> operands added to non read-modify-write partial
definitions. This instruction:

  %reg1234:foo = FLAP %reg1234<imp-def>

will reMaterialize(%reg3333, bar) like this:

  %reg3333:bar-foo = FLAP %reg333:bar<imp-def>

Finally, replace the TargetRegisterInfo pointer argument with a reference to
indicate that it cannot be NULL.

llvm-svn: 105358

definitions of the virtual register.

This happens when spilling the registers produced by REG_SEQUENCE:

%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0

The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.

llvm-svn: 104321

llvm-svn: 103450

doesn't have to guess.

llvm-svn: 103194

llvm-svn: 103193

llvm-svn: 102654

solution.  The only reason these don't fire with gcc-4.2 is that gcc turns off
part of -Wsign-compare in C++ on accident.

llvm-svn: 100581

llvm-svn: 100532

llvm-svn: 99879

llvm-svn: 99637

llvm-svn: 98295

Move methods out of line and M-x whitespace-cleanup.
Promote common method arguments to member variables.

llvm-svn: 98207

Russell Wallace.

llvm-svn: 96580

When coalescing with a physreg, remember to add imp-def and imp-kill when
dealing with sub-registers.

Also fix a related bug in VirtRegRewriter where substitutePhysReg may
reallocate the operand list on an instruction and invalidate the reg_iterator.
This can happen when a register is mentioned twice on the same instruction.

llvm-svn: 96072

llvm-svn: 95748

llvm-svn: 95745

into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687

An instruction like this:

  %reg1097:1<def> = VMOVSR %R3<kill>, 14, %reg0

Must be replaced with this when substituting physical registers:

  %S0<def> = VMOVSR %R3<kill>, 14, %reg0, %D0<imp-def>

llvm-svn: 92812

llvm-svn: 92590

Patch by Howard Hinnant!

llvm-svn: 90365

Fix debug code that assumes getBasicBlock never returns NULL.

llvm-svn: 89428

Fixed the in-place spiller and trivial rewriter, which had been broken by the recent SlotIndexes work.

llvm-svn: 89238

Added getSubRegIndex(A,B) that returns subreg index of A to B. Use it to replace broken code in VirtRegRewriter.

llvm-svn: 88753

- If destination is a physical register and it has a subreg index, use the
  sub-register instead.
This fixes PR5423.

llvm-svn: 88745

llvm-svn: 88738

llvm-svn: 88719

Set the ReloadReuse AsmPrinter flag where appropriate.

llvm-svn: 87030

the second (store) instruction in SpillSlotToUsesMap
consistently.  I don't think this matters functionally,
but it's cleaner and Evan wants it this way.

llvm-svn: 85463

to spill after all, we weren't handling 2-instruction
spill sequences correctly (PPC Altivec).  We need to
remove the store in this case.  Removing the other
instruction(s) would be goodness but is not needed for
correctness, and isn't done here.  7331562.

llvm-svn: 85437

  bootstrapping. It's not safe to leave identity subreg_to_reg and insert_subreg
  around.
- Relax register scavenging to allow use of partially "not-live" registers. It's
  common for targets to operate on registers where the top bits are undef. e.g.
  s0 =
  d0 = insert_subreg d0<undef>, s0, 1
  ...
     = d0
  When the insert_subreg is eliminated by the coalescer, the scavenger used to
  complain. The previous fix was to keep to insert_subreg around. But that's
  brittle and it's overly conservative when we want to use the scavenger to 
  allocate registers. It's actually legal and desirable for other instructions
  to use the "undef" part of d0. e.g.
  s0 =
  d0 = insert_subreg d0<undef>, s0, 1
  ...
  s1 =
     = s1
     = d0
  We probably need add a "partial-undef" marker on machine operand so the
  machine verifier would not complain.

llvm-svn: 85091