doesn't have to guess.

llvm-svn: 103194

llvm-svn: 95781

into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687

llvm-svn: 92596

llvm-svn: 91635

non-landing pad basic block as the successor to a block that ends in an
unconditional jump will cause block folding to remove the added block as a
successor. Thus eventually removing it AND the landing pad entirely. Critical
edge splitting is an optimization, so we can safely turn it off when dealing
with landing pads.

llvm-svn: 91634

This introduces a new pass, SlotIndexes, which is responsible for numbering
instructions for register allocation (and other clients). SlotIndexes numbering
is designed to match the existing scheme, so this patch should not cause any
changes in the generated code.

For consistency, and to avoid naming confusion, LiveIndex has been renamed
SlotIndex.

The processImplicitDefs method of the LiveIntervals analysis has been moved
into its own pass so that it can be run prior to SlotIndexes. This was
necessary to match the existing numbering scheme.

llvm-svn: 85979

VISIBILITY_HIDDEN removal.

llvm-svn: 85043

Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.

llvm-svn: 85042

llvm-svn: 83255

llvm-svn: 83254

Removed static qualifier from a few index related methods. These methods may require a LiveIntervals instance in future.

llvm-svn: 81374

a new class, MachineInstrIndex, which hides arithmetic details from
most clients. This is a step towards allowing the register allocator
to update/insert code during allocation.

llvm-svn: 81040

llvm-svn: 79832

Modified VNInfo. The "copy" member is now a union which holds the copy for a register interval, or the defining register for a stack interval. Access is via getCopy/setCopy and getReg/setReg.

llvm-svn: 78620

llvm-svn: 77754

as an (index,bool) pair. The bool flag records whether the kill is a
PHI kill or not. This code will be used to enable splitting of live
intervals containing PHI-kills.

A slight change to live interval weights introduced an extra spill
into lsr-code-insertion (outside the critical sections). The test 
condition has been updated to reflect this.

llvm-svn: 75097

llvm-svn: 73634

llvm-svn: 72729

llvm-svn: 57424

llvm-svn: 57046

isReg, etc., from isRegister, etc.

llvm-svn: 57006

Use a multimap rather than a map for holding the list of copies to insert, so we don't lose copies when two of them have
the same source.  I don't know what I was thinking when I wrote this originally.
Note: There's probably a more efficient way to do this, but I need to think about it some more, and about what determinism
guarantees need to be present.

llvm-svn: 56964

llvm-svn: 56893

llvm-svn: 56674

llvm-svn: 56567

llvm-svn: 56485

just use LI::MergeValueAsValue, as its behavior in the presence of overlapping ranges
isn't what StrongPHIElimination wants.

llvm-svn: 56472

llvm-svn: 55779

llvm-svn: 54780

llvm-svn: 54742

2) Conditionalize temporary insertion if we don't need it.

llvm-svn: 54741

Do a dominator walk when scheduling copies, rather than a DFS on the CFG.  Also, fix a few problems when creating
live intervals for temporaries created by phi elimination.

llvm-svn: 54483

Correct handle cases where two phis are coalesced together, and correct break up the case where two different
phis want to coalesce with the same vreg.

llvm-svn: 54426

llvm-svn: 54422

llvm-svn: 54421

llvm-svn: 54371

llvm-svn: 54369

Use existing LiveInterval methods to simplify live interval merging.  Thanks to Evan for pointing these out.

llvm-svn: 54225

When merging live intervals, we also need to merge in any live ranges that are inputs to two-address instructions
that themselves define a range we already care about.

llvm-svn: 54185