- Jul 28, 2012
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Eric Christopher authored
all tests accordingly. Fixes PR13351. Patch by shinichiro hamaji! llvm-svn: 160899
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- Jul 27, 2012
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Jakob Stoklund Olesen authored
llvm-svn: 160898
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Chad Rosier authored
llvm-svn: 160897
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Evan Cheng authored
into predecessor blocks to enable tail call optimization. rdar://11958338 llvm-svn: 160894
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Jakob Stoklund Olesen authored
A value number is a PHI def if and only if it begins at a block boundary. This can be derived from the def slot, a separate flag is not necessary. llvm-svn: 160893
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Jakob Stoklund Olesen authored
This option replaces the existing live interval computation with one based on LiveRangeCalc.cpp. The new algorithm does not depend on LiveVariables, and it can be run at any time, before or after leaving SSA form. llvm-svn: 160892
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Andrew Kaylor authored
llvm-svn: 160889
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Jakob Stoklund Olesen authored
Patch by Tyler Nowicki! llvm-svn: 160888
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Benjamin Kramer authored
Also add assertions to validate the iterator in the insert method overloads. llvm-svn: 160882
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Chad Rosier authored
llvm-svn: 160881
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Andrew Kaylor authored
llvm-svn: 160880
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Nuno Lopes authored
llvm-svn: 160876
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Nuno Lopes authored
This can happen as long as the instruction is not reachable. Instcombine does generate these unreachable malformed selects when doing RAUW llvm-svn: 160874
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Andrew Kaylor authored
llvm-svn: 160873
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Jakob Stoklund Olesen authored
Move some functions from MCRegisterInfo.h that don't need to be inline. This shrinks llc by 8K. llvm-svn: 160865
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Benjamin Kramer authored
The rationale here is that it's hard to write loops containing vector erases and it only shows up if the vector contains non-trivial objects leading to crashes when forming them out of garbage memory. llvm-svn: 160854
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Craig Topper authored
llvm-svn: 160852
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Jakob Stoklund Olesen authored
These tables were indexed by [register][subreg index] which made them, very large and sparse. Replace them with lists of sub-register indexes that match the existing lists of sub-registers. MCRI::getSubReg() becomes a very short linear search, like getSubRegIndex() already was. llvm-svn: 160843
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Jakob Stoklund Olesen authored
Now that the weird X86 sub_ss and sub_sd sub-register indexes are gone, there is no longer a need for the CompositeIndices construct in .td files. Sub-register index composition can be specified on the SubRegIndex itself using the ComposedOf field. Also enforce unique names for sub-registers in TableGen. The same sub-register cannot be available with multiple sub-register indexes. llvm-svn: 160842
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Akira Hatanaka authored
replace uses of function getMaxCallFrameSize defined in MipsFunctionInfo with the one MachineFrameInfo has. llvm-svn: 160841
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Pete Cooper authored
llvm-svn: 160835
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Jakob Stoklund Olesen authored
llvm-svn: 160833
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Jakob Stoklund Olesen authored
I'll remove these two sub-register indexes shortly. llvm-svn: 160831
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Jakob Stoklund Olesen authored
The (COPY_TO_REGCLASS GR32:$src, VR128) pattern looks odd, but copyPhysReg does the right thing with it. (The old pattern would eventually produce the same cross-class copy). llvm-svn: 160830
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Pete Cooper authored
llvm-svn: 160823
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Jakob Stoklund Olesen authored
This gets rid of some more INSERT_SUBREG - IMPLICIT_DEF patterns, simplifying the emitted code a bit. llvm-svn: 160820
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Jakob Stoklund Olesen authored
The SUBREG_TO_REG instruction has magic semantics asserting that the source value was defined by an instruction that cleared the high half of the register. Those semantics are never actually exploited for xmm registers. llvm-svn: 160818
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- Jul 26, 2012
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Jakob Stoklund Olesen authored
These idempotent sub-register indices don't do anything --- They simply map XMM registers to themselves. They no longer affect register classes either since the SubRegClasses field has been removed from Target.td. This patch replaces XMM->XMM EXTRACT_SUBREG and INSERT_SUBREG patterns with COPY_TO_REGCLASS patterns which simply become COPY instructions. The number of IMPLICIT_DEF instructions before register allocation is reduced, and that is the cause of the test case changes. llvm-svn: 160816
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Micah Villmow authored
Add support for v16i32/v16i64 into the code generator. This is required for backends that use i32/i64 vectors for the getSetCCResultType function. llvm-svn: 160814
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Chad Rosier authored
Function names should be camel case, and start with a lower case letter. No functional change intended. llvm-svn: 160813
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Jakob Stoklund Olesen authored
llvm-svn: 160798
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Jakob Stoklund Olesen authored
This is still a work in progress. Out-of-order CPUs usually execute instructions from multiple basic blocks simultaneously, so it is necessary to look at longer traces when estimating the performance effects of code transformations. The MachineTraceMetrics analysis will pick a typical trace through a given basic block and provide performance metrics for the trace. Metrics will include: - Instruction count through the trace. - Issue count per functional unit. - Critical path length, and per-instruction 'slack'. These metrics can be used to determine the performance limiting factor when executing the trace, and how it will be affected by a code transformation. Initially, this will be used by the early if-conversion pass. llvm-svn: 160796
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Dan Gohman authored
llvm-svn: 160791
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Nuno Lopes authored
Thanks Eli for noticing. llvm-svn: 160787
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Duncan Sands authored
is a temporary measure until my fix for PR13021 is ready. llvm-svn: 160778
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Duncan Sands authored
llvm-svn: 160777
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Duncan Sands authored
hopefully make it more visible. Adjust the web-docs to have a link to this file rather than the list itself. I described code owners as also being gatekeepers for their part of the code, which I think is true but isn't in the code owner explanation on the web page. llvm-svn: 160776
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Craig Topper authored
llvm-svn: 160775
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Akira Hatanaka authored
Patch by Reed Kotler. llvm-svn: 160774
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Sylvestre Ledru authored
llvm-svn: 160762
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