consistency with other instructions that have lists of register operands.

llvm-svn: 107944

a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.

llvm-svn: 107943

llvm-svn: 107942

disabled and then never turned back on again.  Adjust some tests, one because
this change avoids an unnecessary instruction, and the other to make it
continue testing what it was intended to test.

llvm-svn: 107941

llvm-svn: 107939

llvm-svn: 107937

like all other instructions, even though a segment is not
allowed.  This resolves a bunch of gross hacks in the 
encoder and makes LEA more consistent with the rest of the
instruction set.

No functionality change.

llvm-svn: 107934

llvm-svn: 107930

This reverts commit 107921. It broke the clang self host.

llvm-svn: 107926

X86 memory operand.

llvm-svn: 107925

Relax assertion. In optimized code, it is possible that first instruction is coming from a inlined function.
This fixes PR7596 .

llvm-svn: 107923

if the inline ASM doesn't need a stack frame.

llvm-svn: 107922

llvm-svn: 107921

llvm-svn: 107920

llvm-svn: 107919

in memory operands at the same type as hard coded segments.
This fixes problems where we'd emit the segment override after
the REX prefix on instructions like:
mov %gs:(%rdi), %rax

This fixes rdar://8127102.  I have several cleanup patches coming
next.

llvm-svn: 107917

returns the start of the memory operand for an instruction.

Introduce a new "X86AddrSegment" enum to reduce # magic numbers
referring to X86 memory operand layout.

llvm-svn: 107916

to a Tablegen implementation.

llvm-svn: 107913

.weak_def_can_be_hidden directive.  Chris pointed out that the MCAsmInfo.h/.cpp
chunks aren't needed for this until the compiler starts generating these.  And
when that happens it will be more convenient for it to be a bool than a const
char*.

llvm-svn: 107906

llvm-svn: 107904

Reuse DIEInteger for 1. This is frequently used while emitting an attribute using dwarf::DW_FORM_flag form.

llvm-svn: 107903

This pass runs before COPY instructions are passed to copyPhysReg, so we simply
translate COPY to the proper pseudo instruction. Note that copyPhysReg does not
handle floating point stack copies.

Once COPY is used everywhere, this can be cleaned up a bit, and most of the
pseudo instructions can be removed.

llvm-svn: 107899

llvm-svn: 107898

This pass can go away entirely soon.

llvm-svn: 107892

words within the 64-bit D registers.  Use VLD1/VST1 with 64-bit elements
instead.

llvm-svn: 107890

llvm-svn: 107886

llvm-svn: 107882

the simplification of frame index register scavenging to not have to check
for available registers directly and instead just let scavengeRegister()
handle it.

llvm-svn: 107880

EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.

Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.

llvm-svn: 107879

Fix X86InstrInfo::convertToThreeAddressWithLEA to generate COPY instead of
INSERT_SUBREG.

llvm-svn: 107878

llvm-svn: 107868

(X >s -1) ? C1 : C2 and (X <s  0) ? C2 : C1
into ((X >>s 31) & (C2 - C1)) + C1, avoiding the conditional.

This optimization could be extended to take non-const C1 and C2 but we better
stay conservative to avoid code size bloat for now.

for
int sel(int n) {
     return n >= 0 ? 60 : 100;
}

we now generate
  sarl  $31, %edi
  andl  $40, %edi
  leal  60(%rdi), %eax

instead of
  testl %edi, %edi
  movl  $60, %ecx
  movl  $100, %eax
  cmovnsl %ecx, %eax

llvm-svn: 107866

correct the testcase for valid assembly.

Needs more tests.

llvm-svn: 107860

llvm-svn: 107856

This target hook is intended to replace copyRegToReg entirely, but for now it
calls copyRegToReg.

Any remaining calls to copyRegToReg wil be replaced by COPY instructions.

llvm-svn: 107854

Optimize some vfp comparisons to integer ones. This patch implements the simplest case when the following conditions are met:
1. The arguments are f32.
2. The arguments are loads and they have no uses other than the comparison.
3. The comparison code is EQ or NE.

e.g.
        vldr.32 s0, [r1]
        vldr.32 s1, [r0]
        vcmpe.f32       s1, s0
        vmrs    apsr_nzcv, fpscr
	beq     LBB0_2
=>
        ldr     r1, [r1]
        ldr     r0, [r0]
        cmp     r0, r1
        beq     LBB0_2

More complicated cases will be implemented in subsequent patches.

llvm-svn: 107852

Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.

llvm-svn: 107851

Debug info intrinsics win for now.

llvm-svn: 107850

(if there are any) and use the one which remains available for the longest
rather than just using the first one. This should help enable better re-use
of the loaded frame index values. rdar://7318760

llvm-svn: 107847

address spaces when SRoA'ing memcpy's.

llvm-svn: 107846