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  1. May 12, 2012
    • Akira Hatanaka's avatar
      Make the following changes in MipsAsmPrinter.cpp: · 8f357303
      Akira Hatanaka authored 
      - Remove code which lowers pseudo SETGP01.
- Fix LowerSETGP01. The first two of the three instructions that are emitted to
  initialize the global pointer register now use register $2.
- Stop emitting .cpload directive.

llvm-svn: 156689
      8f357303
    • Akira Hatanaka's avatar
      Insert instructions to the entry basic block which initializes the global · d918f77b
      Akira Hatanaka authored 
      pointer register. 


This is the first of the series of patches which clean up the way global pointer
register is used. The patches will make the following improvements:

- Make $gp an allocatable temporary register rather than reserving it.
- Use a virtual register as the global pointer register and let the register
  allocator decide which register to assign to it or whether spill/reloads are
  needed.
- Make sure $gp is valid at the entry of a called function, which is necessary
  for functions using lazy binding.
- Remove the need for emitting .cprestore and .cpload directives.

llvm-svn: 156671
      d918f77b
    • Akira Hatanaka's avatar
      Do not replace operands of pseudo instructions with register $zero. · 0661b81b
      Akira Hatanaka authored 
      llvm-svn: 156663
      0661b81b
  3. May 11, 2012
  5. May 10, 2012
  7. May 09, 2012
  9. May 08, 2012
  11. May 07, 2012
  13. May 04, 2012
  15. May 01, 2012
  17. Apr 25, 2012
  19. Apr 23, 2012
    • Preston Gurd's avatar
      This patch fixes a problem which arose when using the Post-RA scheduler · 9a091475
      Preston Gurd authored 
      on X86 Atom. Some of our tests failed because the tail merging part of
the BranchFolding pass was creating new basic blocks which did not
contain live-in information. When the anti-dependency code in the Post-RA
scheduler ran, it would sometimes rename the register containing
the function return value because the fact that the return value was
live-in to the subsequent block had been lost. To fix this, it is necessary
to run the RegisterScavenging code in the BranchFolding pass.

This patch makes sure that the register scavenging code is invoked
in the X86 subtarget only when post-RA scheduling is being done.
Post RA scheduling in the X86 subtarget is only done for Atom.

This patch adds a new function to the TargetRegisterClass to control
whether or not live-ins should be preserved during branch folding.
This is necessary in order for the anti-dependency optimizations done
during the PostRASchedulerList pass to work properly when doing
Post-RA scheduling for the X86 in general and for the Intel Atom in particular.

The patch adds and invokes the new function trackLivenessAfterRegAlloc()
instead of using the existing requiresRegisterScavenging().
It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of
requiresRegisterScavenging(). It changes the all the targets that
implemented requiresRegisterScavenging() to also implement
trackLivenessAfterRegAlloc().  

It adds an assertion in the Post RA scheduler to make sure that post RA
liveness information is available when it is needed.

It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order
to avoid running into the added assertion.

Finally, this patch restores the use of anti-dependency checking
(which was turned off temporarily for the 3.1 release) for
Intel Atom in the Post RA scheduler.

Patch by Andy Zhang!

Thanks to Jakob and Anton for their reviews.

llvm-svn: 155395
      9a091475
  21. Apr 22, 2012
  23. Apr 21, 2012
  25. Apr 20, 2012
  27. Apr 18, 2012
  29. Apr 17, 2012
  31. Apr 16, 2012
  33. Apr 12, 2012
  35. Apr 05, 2012
  37. Apr 04, 2012