alignment could lose it due to the alloca type moving down to a much
smaller alignment guarantee.

Now SROA will actively compute a proper alignment, factoring the target
data, any explicit alignment, and the offset within the struct. This
will in some cases lower the alignment requirements, but when we lower
them below those of the type, we drop the alignment entirely to give
freedom to the code generator to align it however is convenient.

Thanks to Duncan for the lovely test case that pinned this down. =]

llvm-svn: 164891

buildbots.  Original commit message:

A DAGCombine optimization for merging consecutive stores. This optimization is not profitable in many cases
because moden processos can store multiple values in parallel, and preparing the consecutive store requires
some work.  We only handle these cases:

1. Consecutive stores where the values and consecutive loads. For example:
  int a = p->a;
  int b = p->b;
  q->a = a;
  q->b = b;

2. Consecutive stores where the values are constants. Foe example:
  q->a = 4;
  q->b = 5;

llvm-svn: 164890

Tidy up to match coding standards. Remove 'else' after 'return' and moving operators to end of preceding line. No functional change intended.

llvm-svn: 164887

Replace a couple if/elses around similar calls with conditional operators on the varying arguments. No functional change.

llvm-svn: 164886

A DAGCombine optimization for merging consecutive stores. This optimization is not profitable in many cases
because moden processos can store multiple values in parallel, and preparing the consecutive store requires
some work.  We only handle these cases:

1. Consecutive stores where the values and consecutive loads. For example:
  int a = p->a;
  int b = p->b;
  q->a = a;
  q->b = b;

2. Consecutive stores where the values are constants. Foe example:
  q->a = 4;
  q->b = 5;

llvm-svn: 164885

llvm-svn: 164880

llvm-svn: 164867

llvm-svn: 164866

llvm-svn: 164860

llvm-svn: 164850

llvm-svn: 164849

llvm-svn: 164848

In reStructuredText, indented blocks denote block quotes [1]. This list
is not a block quote.

[1]. http://docutils.sourceforge.net/docs/ref/rst/restructuredtext.html#block-quotes

llvm-svn: 164847

llvm-svn: 164845

llvm-svn: 164842

llvm-svn: 164840

second output of SUB with first output of TEST.

PR13966

llvm-svn: 164835

Patch committed on behalf of Kirill Uhanov

llvm-svn: 164831

llvm-svn: 164826

llvm-svn: 164823

Patch by Martinez, Javier E.

llvm-svn: 164822

CorrelatedPropagation: BasicBlock::removePredecessor can simplify PHI nodes. If the it's the condition of a SwitchInst, reload it.

Fixes PR13972.

llvm-svn: 164818

llvm-svn: 164817

Fixes PR13968.

llvm-svn: 164815

llvm-svn: 164814

llvm-svn: 164813

2. As part of this, added assembly format FEXT_RI16_SP_explicit_ins and
moved other lines for FEXT_RI16 formats to be in the right place in the code.
3. Added mayLoad and mayStore assignements for the load/store instructions added and for ones already there that did not have this assignment.
4. Another patch will deal with the problem of load/store byte/halfword to the stack. This is a particular Mips16 problem.

llvm-svn: 164811

The new coalescer can turn a full virtual register definition into a
partial redef by merging another value into an unused vector lane.

Make sure to clear the <read-undef> flag on such defs.

llvm-svn: 164807

llvm-svn: 164805

llvm-svn: 164800

llvm-svn: 164799

llvm-svn: 164798

llvm-svn: 164797

llvm-svn: 164796

The new coalescer is better at merging values into unused vector lanes,
improving NEON code.

llvm-svn: 164794

The fix is obvious and the only test case I have is horrible, so I am
not including it. The problem shows up when self-hosting clang on i386
with -new-coalescer enabled.

llvm-svn: 164793

llvm-svn: 164787

llvm-svn: 164786

If the width is very large it gets truncated from uint64_t to uint32_t when
passed to TD->fitsInLegalInteger. The truncated value can fit in a register.
This manifested in massive memory usage or crashes (PR13946).

llvm-svn: 164784

llvm-svn: 164782