copied-in constant, as a subsequent user may rely on over alignment.
Fixes PR12885.

llvm-svn: 157134

The current code will generate a prologue which starts with something like:
        mflr 0
        stw 31, -4(1)
        stw 0, 4(1)
        stwu 1, -16(1)

But under the PPC32 SVR4 ABI, access to negative offsets from R1 is not allowed.

This was pointed out by Peter Bergner.

llvm-svn: 157133

Dead code and joined copies are now eliminated on the fly, and there is
no need for a post pass.

This makes the coalescer work like other modern register allocator
passes: Code is changed on the fly, there is no pending list of changes
to be committed.

llvm-svn: 157132

The late dead code elimination is no longer necessary.

The test changes are cause by a register hint that can be either %rdi or
%rax. The choice depends on the use list order, which this patch changes.

llvm-svn: 157131

Before rewriting uses of one value in A to register B, check that there
are no tied uses. That would require multiple A values to be rewritten.

This bug can't bite in the current version of the code for a fairly
subtle reason: A tied use would have caused 2-addr to insert a copy
before the use. If the copy has been coalesced, it will be found by the
same loop changed by this patch, and the optimization is aborted.

This was exposed by 400.perlbench and lua after applying a patch that
deletes joined copies aggressively.

llvm-svn: 157130

llvm-svn: 157129

llvm-svn: 157127

clang++ and msvc happily had no problem with it but g++ refuses to compile.

llvm-svn: 157126

There is no reason to defer the collection of virtual registers whose
register class may be replaced with a larger class.

llvm-svn: 157125

Otherwise just looking up a value in the map requires creating a VH, adding it to the use lists and destroying it again.

llvm-svn: 157124

Move CallbackVHs dtor inline, it can be devirtualized in many cases. Move the other virtual methods out of line as they are only called from within Value.cpp anyway.

llvm-svn: 157123

llvm-svn: 157122

llvm-svn: 157118

This makes DenseMap<..., TinyPtrVector<...>> as cheap as it always should've been!

llvm-svn: 157113

llvm-svn: 157112

llvm-svn: 157109

This will remove the original def once it has no more uses.

llvm-svn: 157104

Remaining virtreg->physreg copies were rematerialized during
updateRegDefsUses(), but we already do the same thing in joinCopy() when
visiting the physreg copy instruction.

Eliminate the preserveSrcInt argument to reMaterializeTrivialDef(). It
is now always true.

llvm-svn: 157103

There is no need for these instructions to stick around since they are
known to be not dead.

llvm-svn: 157102

Dead copies cause problems because they are trivial to coalesce, but
removing them gived the live range a dangling end point. This patch
enables full dead code elimination which trims live ranges to their uses
so end points don't dangle.

DCE may erase multiple instructions. Put the pointers in an ErasedInstrs
set so we never risk visiting erased instructions in the work list.

There isn't supposed to be any dead copies entering RegisterCoalescer,
but they do slip by as evidenced by test/CodeGen/X86/coalescer-dce.ll.

llvm-svn: 157101

The dead code elimination with callbacks is still useful.

llvm-svn: 157100

to generate out of the front end.

rdar://11479676

llvm-svn: 157094

Patch by Jack Carter.

llvm-svn: 157093

getUDivExpr attempts to simplify by checking for overflow.
isLoopEntryGuardedByCond then evaluates the loop predicate which
may lead to the same getUDivExpr causing endless recursion.

Fixes PR12868: clang 3.2 segmentation fault.

llvm-svn: 157092

when deleting them. rdar://11434915.

llvm-svn: 157080

No functional change.

llvm-svn: 157079

This will make it possible to filter out erased instructions later.

llvm-svn: 157073

allow LazyValueInfo::getEdgeValue() to reason about multiple edges from the same switch instruction by doing union of ranges (which may still be conservative, but it's more aggressive than before)

llvm-svn: 157071

Use a dedicated MachO load command to annotate data-in-code regions.
This is the same format the linker produces for final executable images,
allowing consistency of representation and use of introspection tools
for both object and executable files.

Data-in-code regions are annotated via ".data_region"/".end_data_region"
directive pairs, with an optional region type.

data_region_directive := ".data_region" { region_type }
region_type := "jt8" | "jt16" | "jt32" | "jta32"
end_data_region_directive := ".end_data_region"

The previous handling of ARM-style "$d.*" labels was broken and has
been removed. Specifically, it didn't handle ARM vs. Thumb mode when
marking the end of the section.

rdar://11459456

llvm-svn: 157062

llvm-svn: 157061

llvm-svn: 157060

It is no longer necessary to separate VirtCopies, PhysCopies, and
ImpDefCopies. Implicitly defined copies are extremely rare after we
added the ProcessImplicitDefs pass, and physical register copies are not
joined any longer.

llvm-svn: 157059

llvm-svn: 157058

Patch by Jack Carter.

llvm-svn: 157057

This has been disabled for a while, and it is not a feature we want to
support. Copies between physical and virtual registers are eliminated by
good hinting support in the register allocator. Joining virtual and
physical registers is really a form of register allocation, and the
coalescer is not properly equipped to do that. In particular, it cannot
backtrack coalescing decisions, and sometimes that would cause it to
create programs that were impossible to register allocate, by exhausting
a small register class.

It was also very difficult to keep track of the live ranges of aliasing
registers when extending the live range of a physreg. By disabling
physreg joining, we can let fixed physreg live ranges remain constant
throughout the register allocator super-pass.

One type of physreg joining remains: A virtual register that has a
single value which is a copy of a reserved register can be merged into
the reserved physreg. This always lowers register pressure, and since we
don't compute live ranges for reserved registers, there are no problems
with aliases.

llvm-svn: 157055

llvm-svn: 157051

SelectionDAGBuilder::Clusterify : main functinality was replaced with CRSBuilder::optimize, so big part of Clusterify's code was reduced.

llvm-svn: 157046

llvm-svn: 157044

llvm-svn: 157043

non-profitable commute using outdated info. The test case would still fail
because of poor pre-RA schedule. That will be fixed by MI scheduler.

rdar://11472010

llvm-svn: 157038