Commits · 9e369f2a510a6f3b014fd8e6e2dd5e054f7735e9 · Roger Ferrer / llvm-epi-0.8 · GitLab

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Feb 06, 2016
- [X86][SSE] Don't replace an existing 32-bit load with its duplicate · 9e369f2a
  Simon Pilgrim authored Feb 06, 2016
  9e369f2a
- Comment fix · 11e4d114
  Simon Pilgrim authored Feb 06, 2016
  11e4d114
- New Loop Versioning LICM Pass · df6763ab
  Ashutosh Nema authored Feb 06, 2016
  df6763ab
- Relax assertion in ReplaceableMetadataImpl::replaceAllUsesWith(). · b925b9c8
  Adrian Prantl authored Feb 06, 2016
  b925b9c8
- [Orc] Slightly improve the x86-64 resolver block machine code. · 120a9b41
  Lang Hames authored Feb 06, 2016
  120a9b41
- [AArch64] Add the scheduling model for Exynos-M1 · d761ca23
  Evandro Menezes authored Feb 06, 2016
  d761ca23
- [StatepointLower] Use None instead of Optional<int>() · 86d7d83f
  Sanjoy Das authored Feb 05, 2016
  86d7d83f
- [Orc] Fix a typo in the comments for the x86_64 resolver block. · d677fa83
  Lang Hames authored Feb 05, 2016
  d677fa83
- Attempt#2 to work around MSVC rejects-valid. · ef9ac7a5
  Richard Smith authored Feb 05, 2016
  ef9ac7a5
Feb 05, 2016
- More workarounds for undefined behavior exposed when compiling in C++14 with · ebfdf26d
  Richard Smith authored Feb 05, 2016
  ebfdf26d
- CallAnalyzer::analyzeCall: change the condition back to "Cost < Threshold" · 00ab73dc
  Hans Wennborg authored Feb 05, 2016
  00ab73dc
- [AArch64] Refactoring aarch64-ldst-opt. NCF. · 1de2d44d
  Jun Bum Lim authored Feb 05, 2016
  1de2d44d
- AMDGPU: Account for LDS alignment · 7f83397d
  Matt Arsenault authored Feb 05, 2016
  7f83397d
- AMDGPU: Preserve alignments on new created globals · cf84e26f
  Matt Arsenault authored Feb 05, 2016
  cf84e26f
- AMDGPU: Remove some purely R600 functions from AMDGPUInstrInfo · 1242ce96
  Tom Stellard authored Feb 05, 2016
  1242ce96
- AMDGPU: Fix ordering of CPU and FS parameters in TargetMachine constructors · 5dde1d2e
  Tom Stellard authored Feb 05, 2016
  5dde1d2e
- Some stackslots are allocated to vregs which have no real reference. · a62f0589
  Wei Mi authored Feb 05, 2016
  a62f0589
- AMDGPU/SI: Correctly initialize SIInsertWaits pass · 6e1967ef
  Tom Stellard authored Feb 05, 2016
  6e1967ef
- [WebAssembly] Update the select instructions' operand orders to match the spec. · d46b0926
  Dan Gohman authored Feb 05, 2016
  d46b0926
- Fix for PR 26193 · d389c7a3
  Nemanja Ivanovic authored Feb 05, 2016
  d389c7a3
- Move classes defined in a cpp file into an anonymous namespace. · 85c824f1
  Benjamin Kramer authored Feb 05, 2016
  85c824f1
- Revert "[AArch64] Improve load/store optimizer to handle LDUR + LDR (take 3)." · 6274e522
  Renato Golin authored Feb 05, 2016
  6274e522
- [DebugInfo] Eliminate compilation warning about used variable LSDA · f4124a72
  Dmitry Polukhin authored Feb 05, 2016
  f4124a72
- [LoopUnrolling] Try harder to avoid rebuilding LCSSA when possible. · 73957179
  Michael Zolotukhin authored Feb 05, 2016
  73957179
- [MC] Add support for encoding CodeView variable definition ranges · 408b5e66
  David Majnemer authored Feb 05, 2016
  408b5e66
- [RS4GC] Pass DenseMap by reference, NFC · adc23763
  Joseph Tremoulet authored Feb 05, 2016
  adc23763
- [LoopLoadElim] Don't allow versioning when optForSize · 9455c1d2
  Adam Nemet authored Feb 05, 2016
  9455c1d2
- Fix printing of f16 machine operands · 5923973f
  Matt Arsenault authored Feb 05, 2016
  5923973f
- Function name change /NFC · eb7d7f87
  Xinliang David Li authored Feb 04, 2016
  eb7d7f87
- Refactor profile summary support code. NFC. · d68aae24
  Easwaran Raman authored Feb 04, 2016
  d68aae24
- Fix for PR 26356 · b6fdce4c
  Nemanja Ivanovic authored Feb 04, 2016
  b6fdce4c
Feb 04, 2016
- [AArch64] Bound the number of instructions we scan when searching for updates. · 35706ad6
  Chad Rosier authored Feb 04, 2016
  35706ad6
- [X86][SSE] Select domain for 32/64-bit partial loads for EltsFromConsecutiveLoads · 7823fd25
  Simon Pilgrim authored Feb 04, 2016
  7823fd25
- Fix a regression for r259736. · 33e7bc00
  Wei Mi authored Feb 04, 2016
  33e7bc00
- [PGO] Add interfaces to annotate instr with VP data · 402477d2
  Xinliang David Li authored Feb 04, 2016
  402477d2
- [AArch64] Improve load/store optimizer to handle LDUR + LDR (take 3). · 05f8020c
  Chad Rosier authored Feb 04, 2016
  05f8020c
- [SCEV] Add boolean accessors for NSW, NUW and NW; NFC · 76c48e0e
  Sanjoy Das authored Feb 04, 2016
  76c48e0e
- [AArch64] Multiply extended 32-bit ints with `[U|S]MADDL' · 33b3bd17
  Silviu Baranga authored Feb 04, 2016
  33b3bd17
- Enable the %s modifier in inline asm template string · e8cbae32
  Nemanja Ivanovic authored Feb 04, 2016
  e8cbae32
- [X86][SSE] Add general 32-bit LOAD + VZEXT_MOVL support to EltsFromConsecutiveLoads · 6788f33c
  Simon Pilgrim authored Feb 04, 2016
  6788f33c