It was renamed in gcc/gas a while ago and causes all kinds of
confusion because it was named differently in llvm and clang.

llvm-svn: 157745

be non contiguous, non overlapping and sorted by the lower end.

While this is technically a backward incompatibility, every frontent currently
produces range metadata with a single interval and we don't have any pass
that merges intervals yet, so no existing bitcode files should be rejected by
this.

llvm-svn: 157741

I disabled FMA3 autodetection, since the result may differ from expected for some benchmarks.
I added tests for GodeGen and intrinsics.
I did not change llvm.fma.f32/64 - it may be done later.

llvm-svn: 157737

Carlo Alberto Ferraris.

llvm-svn: 157736

llvm-svn: 157731

CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16
jalr instruction.

Patch by Reed Kotler.

llvm-svn: 157730

llvm-svn: 157726

llvm-svn: 157725

This code is covered by test/CodeGen/ARM/arm-modifier.ll.

llvm-svn: 157720

Switch to MCSuperRegIterator while we're there.

llvm-svn: 157717

It helps compile exotic inline asm. In the test case, normal GR32
virtual registers use up eax-edx so the final GR32_ABCD live range has
no registers left. Since all the live ranges were tiny, we had no way of
prioritizing the smaller register class.

This patch allows tiny unspillable live ranges to be evicted by tiny
unspillable live ranges from a smaller register class.

<rdar://problem/11542429>

llvm-svn: 157715

It seems I broke C++11.

llvm-svn: 157711

Patch by Jack Carter.

llvm-svn: 157709

Switch the canonical FMA term operand order to match both the comment I wrote and the usual LLVM convention.

llvm-svn: 157708

llvm-svn: 157707

llvm-svn: 157706

This broke in r144788 when the CodeGenOpt option was moved from everywhere else
(specifically, from addPassesToEmitFile) to createTargetMachine. Since
LTOCodeGenerator wasn't passing the 4th argument, when the 4th parameter became
the 3rd, it silently continued to compile (int->bool conversion) but meant
something completely different.

This change preserves the existing (accidental) and previous (default)
semantics of the addPassesToEmitFile and restores the previous/intended
CodeGenOpt argument by passing it appropriately to createTargetMachine.

(discovered by pending changes to -Wconversion to catch constant->bool
conversions)

llvm-svn: 157705

llvm-svn: 157704

It is better to address sub-registers directly by name instead of
relying on their position in the sub-register list.

llvm-svn: 157703

An empty list is not represented as a null pointer. Let TRI do its own
shortcuts.

llvm-svn: 157702

This also required making recursive simplifications until
nothing changes or a hard limit (currently 3) is hit.

With the simplification in place indvars can canonicalize
loops of the form
for (unsigned i = 0; i < a-b; ++i)
into
for (unsigned i = 0; i != a-b; ++i)
which used to fail because SCEV created a weird umax expr
for the backedge taken count.

llvm-svn: 157701

it's pointed out that R11 can be used for magic things, and doing things just for 64-bit registers is silly.  Just optimize 3 more.

llvm-svn: 157699

integer registers.  This is already supported by the fastcc convention, but it doesn't
hurt to support it in the standard conventions as well.

In cases where we can cheat at the calling convention, this allows us to avoid returning
things through memory in more cases.

llvm-svn: 157698

Patch by Jush Lu <jush.msn@gmail.com>.

llvm-svn: 157696

Also add subclasses MCSubRegIterator, MCSuperRegIterator, and
MCRegAliasIterator.

These iterators provide an abstract interface to the MCRegisterInfo
register lists so the internal representation can be changed without
changing all clients.

llvm-svn: 157695

llvm-svn: 157688

llvm-svn: 157685

llvm-svn: 157684

llvm-svn: 157683

If integer overflow causes one of the terms to reach zero, that can
force the entire expression to zero.

Fixes PR12929: cast<Ty>() argument of incompatible type

llvm-svn: 157673

No functionality.

llvm-svn: 157672

llvm-svn: 157663

If-converter models predicated defs as read + write. The read should be marked as 'undef' since it may not already be live. This appeases -verify-machineinstrs.

llvm-svn: 157662

llvm-svn: 157661

Besides adding the new insertPass function, this patch uses it to
enhance the existing -print-machineinstrs so that the MachineInstrs
after a specific pass can be printed.

Patch by Bin Zeng!

llvm-svn: 157655

Apparently, a friend can't derive from a private class according to gcc.

llvm-svn: 157654

The register unit lists are typically much shorter than the register
overlap lists, and the backing table for register units has better cache
locality because it is smaller.

This makes llc about 0.5% faster. The regsOverlap() function isn't that hot.

llvm-svn: 157651

Register units are already used internally in TableGen to compute
register pressure sets and overlapping registers. This patch makes them
available to the code generators.

The register unit lists are differentially encoded so they can be reused
for many related registers. This keeps the total size of the lists below
200 bytes for most targets. ARM has the largest table at 560 bytes.

Add an MCRegUnitIterator for traversing the register unit lists. It
provides an abstract interface so the representation can be changed in
the future without changing all clients.

llvm-svn: 157650

 - hoist checks out of loops where SCEV is smart enough
 - add additional statistics to measure how much we loose for not supporting interprocedural and pointers loaded from memory

llvm-svn: 157649

llvm-svn: 157644