llvm-svn: 157155

llvm-svn: 157152

They need to go on the PICLDR as the verifier points out.

llvm-svn: 157151

Not all GR64 registers have sub_8bit sub-registers.

llvm-svn: 157150

X86 has 2-addr instructions with different constraints on the tied def
and use operands. One is GR32, one is GR32_NOSP.

llvm-svn: 157149

llvm-svn: 157148

This function adds copies to be erased to DupCopies, avoid also adding
them to DeadCopies.

llvm-svn: 157147

Avoid looking at the operands of a potentially erased instruction.

llvm-svn: 157146

llvm-svn: 157145

llvm-svn: 157144

That struct ought to be a LiveInterval implementation detail.

llvm-svn: 157143

llvm-svn: 157142

LoopUnswitch.  Fixes PR12887.

llvm-svn: 157140

llvm-svn: 157137

Dead code elimination during coalescing could cause a virtual register
to be split into connected components. The following rewriting would be
confused about the already joined copies present in the code, but
without a corresponding value number in the live range.

Erase all joined copies instantly when joining intervals such that the
MI and LiveInterval representations are always in sync.

llvm-svn: 157135

copied-in constant, as a subsequent user may rely on over alignment.
Fixes PR12885.

llvm-svn: 157134

The current code will generate a prologue which starts with something like:
        mflr 0
        stw 31, -4(1)
        stw 0, 4(1)
        stwu 1, -16(1)

But under the PPC32 SVR4 ABI, access to negative offsets from R1 is not allowed.

This was pointed out by Peter Bergner.

llvm-svn: 157133

Dead code and joined copies are now eliminated on the fly, and there is
no need for a post pass.

This makes the coalescer work like other modern register allocator
passes: Code is changed on the fly, there is no pending list of changes
to be committed.

llvm-svn: 157132

The late dead code elimination is no longer necessary.

The test changes are cause by a register hint that can be either %rdi or
%rax. The choice depends on the use list order, which this patch changes.

llvm-svn: 157131

Before rewriting uses of one value in A to register B, check that there
are no tied uses. That would require multiple A values to be rewritten.

This bug can't bite in the current version of the code for a fairly
subtle reason: A tied use would have caused 2-addr to insert a copy
before the use. If the copy has been coalesced, it will be found by the
same loop changed by this patch, and the optimization is aborted.

This was exposed by 400.perlbench and lua after applying a patch that
deletes joined copies aggressively.

llvm-svn: 157130

llvm-svn: 157129

llvm-svn: 157127

There is no reason to defer the collection of virtual registers whose
register class may be replaced with a larger class.

llvm-svn: 157125

Move CallbackVHs dtor inline, it can be devirtualized in many cases. Move the other virtual methods out of line as they are only called from within Value.cpp anyway.

llvm-svn: 157123

llvm-svn: 157122

llvm-svn: 157112

llvm-svn: 157109

This will remove the original def once it has no more uses.

llvm-svn: 157104

Remaining virtreg->physreg copies were rematerialized during
updateRegDefsUses(), but we already do the same thing in joinCopy() when
visiting the physreg copy instruction.

Eliminate the preserveSrcInt argument to reMaterializeTrivialDef(). It
is now always true.

llvm-svn: 157103

There is no need for these instructions to stick around since they are
known to be not dead.

llvm-svn: 157102

Dead copies cause problems because they are trivial to coalesce, but
removing them gived the live range a dangling end point. This patch
enables full dead code elimination which trims live ranges to their uses
so end points don't dangle.

DCE may erase multiple instructions. Put the pointers in an ErasedInstrs
set so we never risk visiting erased instructions in the work list.

There isn't supposed to be any dead copies entering RegisterCoalescer,
but they do slip by as evidenced by test/CodeGen/X86/coalescer-dce.ll.

llvm-svn: 157101

The dead code elimination with callbacks is still useful.

llvm-svn: 157100

to generate out of the front end.

rdar://11479676

llvm-svn: 157094

Patch by Jack Carter.

llvm-svn: 157093

getUDivExpr attempts to simplify by checking for overflow.
isLoopEntryGuardedByCond then evaluates the loop predicate which
may lead to the same getUDivExpr causing endless recursion.

Fixes PR12868: clang 3.2 segmentation fault.

llvm-svn: 157092

when deleting them. rdar://11434915.

llvm-svn: 157080

No functional change.

llvm-svn: 157079

This will make it possible to filter out erased instructions later.

llvm-svn: 157073

allow LazyValueInfo::getEdgeValue() to reason about multiple edges from the same switch instruction by doing union of ranges (which may still be conservative, but it's more aggressive than before)

llvm-svn: 157071

Use a dedicated MachO load command to annotate data-in-code regions.
This is the same format the linker produces for final executable images,
allowing consistency of representation and use of introspection tools
for both object and executable files.

Data-in-code regions are annotated via ".data_region"/".end_data_region"
directive pairs, with an optional region type.

data_region_directive := ".data_region" { region_type }
region_type := "jt8" | "jt16" | "jt32" | "jta32"
end_data_region_directive := ".end_data_region"

The previous handling of ARM-style "$d.*" labels was broken and has
been removed. Specifically, it didn't handle ARM vs. Thumb mode when
marking the end of the section.

rdar://11459456

llvm-svn: 157062