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  1. Aug 24, 2012
  2. Aug 06, 2012
  3. Jul 19, 2012
  4. Jul 02, 2012
  5. Jun 26, 2012
    • Jack Carter's avatar
      There are a number of generic inline asm operand modifiers that · 5e69cffe
      Jack Carter authored
      up to r158925 were handled as processor specific. Making them 
      generic and putting tests for these modifiers in the CodeGen/Generic
      directory caused a number of targets to fail. 
      
      This commit addresses that problem by having the targets call 
      the generic routine for generic modifiers that they don't currently
      have explicit code for.
      
      For now only generic print operands 'c' and 'n' are supported.vi
      
      
      Affected files:
      
          test/CodeGen/Generic/asm-large-immediate.ll
          lib/Target/PowerPC/PPCAsmPrinter.cpp
          lib/Target/NVPTX/NVPTXAsmPrinter.cpp
          lib/Target/ARM/ARMAsmPrinter.cpp
          lib/Target/XCore/XCoreAsmPrinter.cpp
          lib/Target/X86/X86AsmPrinter.cpp
          lib/Target/Hexagon/HexagonAsmPrinter.cpp
          lib/Target/CellSPU/SPUAsmPrinter.cpp
          lib/Target/Sparc/SparcAsmPrinter.cpp
          lib/Target/MBlaze/MBlazeAsmPrinter.cpp
          lib/Target/Mips/MipsAsmPrinter.cpp
          
      MSP430 isn't represented because it did not even run with
      the long existing 'c' modifier and it was not apparent what
      needs to be done to get it inline asm ready.
      
      Contributer: Jack Carter
      llvm-svn: 159203
      5e69cffe
  6. Jun 24, 2012
  7. Jun 06, 2012
  8. Jun 01, 2012
  9. May 25, 2012
  10. May 04, 2012
  11. May 01, 2012
  12. Apr 20, 2012
  13. Apr 04, 2012
    • Rafael Espindola's avatar
      Always compute all the bits in ComputeMaskedBits. · ba0a6cab
      Rafael Espindola authored
      This allows us to keep passing reduced masks to SimplifyDemandedBits, but
      know about all the bits if SimplifyDemandedBits fails. This allows instcombine
      to simplify cases like the one in the included testcase.
      
      llvm-svn: 154011
      ba0a6cab
  14. Mar 27, 2012
  15. Mar 22, 2012
  16. Mar 17, 2012
  17. Mar 11, 2012
  18. Mar 04, 2012
  19. Feb 28, 2012
  20. Feb 19, 2012
  21. Feb 18, 2012
  22. Feb 07, 2012
  23. Feb 05, 2012
  24. Feb 04, 2012
    • Andrew Trick's avatar
      TargetPassConfig: confine the MC configuration to TargetMachine. · f8ea108c
      Andrew Trick authored
      Passes prior to instructon selection are now split into separate configurable stages.
      Header dependencies are simplified.
      The bulk of this diff is simply removal of the silly DisableVerify flags.
      
      Sorry for the target header churn. Attempting to stabilize them.
      
      llvm-svn: 149754
      f8ea108c
  25. Feb 03, 2012
    • Andrew Trick's avatar
      Added TargetPassConfig. The first little step toward configuring codegen passes. · ccb67365
      Andrew Trick authored
      Allows command line overrides to be centralized in LLVMTargetMachine.cpp.
      LLVMTargetMachine can intercept common passes and give precedence to command line overrides.
      Allows adding "internal" target configuration options without touching TargetOptions.
      Encapsulates the PassManager.
      Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs.
      Allows modifying the target configuration hooks without rebuilding the world.
      
      llvm-svn: 149672
      ccb67365
  26. Jan 20, 2012
  27. Jan 18, 2012
    • Jakob Stoklund Olesen's avatar
      Add a CoveredBySubRegs property to Register descriptions. · f43b5995
      Jakob Stoklund Olesen authored
      When set, this bit indicates that a register is completely defined by
      the value of its sub-registers.
      
      Use the CoveredBySubRegs property to infer which super-registers are
      call-preserved given a list of callee-saved registers.  For example, the
      ARM registers D8-D15 are callee-saved.  This now automatically implies
      that Q4-Q7 are call-preserved.
      
      Conversely, Win64 callees save XMM6-XMM15, but the corresponding
      YMM6-YMM15 registers are not call-preserved because they are not fully
      defined by their sub-registers.
      
      llvm-svn: 148363
      f43b5995
  28. Jan 10, 2012
  29. Jan 07, 2012
  30. Dec 25, 2011
  31. Dec 20, 2011
  32. Dec 13, 2011
    • Chandler Carruth's avatar
      Initial CodeGen support for CTTZ/CTLZ where a zero input produces an · 637cc6a8
      Chandler Carruth authored
      undefined result. This adds new ISD nodes for the new semantics,
      selecting them when the LLVM intrinsic indicates that the undef behavior
      is desired. The new nodes expand trivially to the old nodes, so targets
      don't actually need to do anything to support these new nodes besides
      indicating that they should be expanded. I've done this for all the
      operand types that I could figure out for all the targets. Owners of
      various targets, please review and let me know if any of these are
      incorrect.
      
      Note that the expand behavior is *conservatively correct*, and exactly
      matches LLVM's current behavior with these operations. Ideally this
      patch will not change behavior in any way. For example the regtest suite
      finds the exact same instruction sequences coming out of the code
      generator. That's why there are no new tests here -- all of this is
      being exercised by the existing test suite.
      
      Thanks to Duncan Sands for reviewing the various bits of this patch and
      helping me get the wrinkles ironed out with expanding for each target.
      Also thanks to Chris for clarifying through all the discussions that
      this is indeed the approach he was looking for. That said, there are
      likely still rough spots. Further review much appreciated.
      
      llvm-svn: 146466
      637cc6a8
  33. Dec 12, 2011
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