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  1. Oct 15, 2012
  2. Oct 14, 2012
  3. Oct 13, 2012
    • Jakob Stoklund Olesen's avatar
      Drop <def,dead> flags when merging into an unused lane. · ea82bd7f
      Jakob Stoklund Olesen authored
      The new coalescer can merge a dead def into an unused lane of an
      otherwise live vector register.
      
      Clear the <dead> flag when that happens since the flag refers to the
      full virtual register which is still live after the partial dead def.
      
      This fixes PR14079.
      
      llvm-svn: 165877
      ea82bd7f
    • Jakob Stoklund Olesen's avatar
      Allow for loops in LiveIntervals::pruneValue(). · 2f6dfc7d
      Jakob Stoklund Olesen authored
      It is possible that the live range of the value being pruned loops back
      into the kill MBB where the search started. When that happens, make sure
      that the beginning of KillMBB is also pruned.
      
      Instead of starting a DFS at KillMBB and skipping the root of the
      search, start a DFS at each KillMBB successor, and allow the search to
      loop back to KillMBB.
      
      This fixes PR14078.
      
      llvm-svn: 165872
      2f6dfc7d
  4. Oct 12, 2012
    • Jakob Stoklund Olesen's avatar
      Use a transposed algorithm for handleMove(). · 1a87a29d
      Jakob Stoklund Olesen authored
      Completely update one interval at a time instead of collecting live
      range fragments to be updated. This avoids building data structures,
      except for a single SmallPtrSet of updated intervals.
      
      Also share code between handleMove() and handleMoveIntoBundle().
      
      Add support for moving dead defs across other live values in the
      interval. The MI scheduler can do that.
      
      llvm-svn: 165824
      1a87a29d
    • Jakob Stoklund Olesen's avatar
      Fix coalescing with IMPLICIT_DEF values. · 1a3eb878
      Jakob Stoklund Olesen authored
      PHIElimination inserts IMPLICIT_DEF instructions to guarantee that all
      PHI predecessors have a live-out value. These IMPLICIT_DEF values are
      not considered to be real interference when coalescing virtual
      registers:
      
        %vreg1 = IMPLICIT_DEF
        %vreg2 = MOV32r0
      
      When joining %vreg1 and %vreg2, the IMPLICIT_DEF instruction and its
      value number should simply be erased since the %vreg2 value number now
      provides a live-out value for the PHI predecesor block.
      
      llvm-svn: 165813
      1a3eb878
    • Ulrich Weigand's avatar
      Fix big-endian codegen bug in DAGTypeLegalizer::ExpandRes_BITCAST · 9aa51d1a
      Ulrich Weigand authored
      On PowerPC, a bitcast of <16 x i8> to i128 may run through a code
      path in ExpandRes_BITCAST that attempts to do an intermediate
      bitcast to a <4 x i32> vector, and then construct the Hi and Lo parts
      of the resulting i128 by pairing up two of those i32 vector elements
      each.  The code already recognizes that on a big-endian system, the
      first two vector elements form the Hi part, and the final two vector
      elements form the Lo part (vice-versa from the little-endian situation).
      
      However, we also need to take endianness into account when forming each
      of those separate pairs:  on a big-endian system, vector element 0 is
      the *high* part of the pair making up the Hi part of the result, and
      vector element 1 is the low part of the pair.  The code currently always
      uses vector element 0 as the low part and vector element 1 as the high
      part, as is appropriate for little-endian platforms only.
      
      This patch fixes this by swapping the vector elements as they are
      paired up as appropriate.
      
      llvm-svn: 165802
      9aa51d1a
    • Evan Cheng's avatar
      Legalizer optimize a pair of div / mod to a call to divrem libcall if they are · 21c4adcd
      Evan Cheng authored
      not legal. However, it should use a div instruction + mul + sub if divide is
      legal. The rem legalization code was missing a check and incorrectly uses a
      divrem libcall even when div is legal.
      
      rdar://12481395
      
      llvm-svn: 165778
      21c4adcd
    • Sean Silva's avatar
      Remove unnecessary classof()'s · 506a1c5a
      Sean Silva authored
      isa<> et al. automatically infer when the cast is an upcast (including a
      self-cast), so these are no longer necessary.
      
      llvm-svn: 165767
      506a1c5a
  5. Oct 11, 2012
  6. Oct 10, 2012
    • Micah Villmow's avatar
      Add in support for expansion of all of the comparison operations to the... · 0242b9b5
      Micah Villmow authored
      Add in support for expansion of all of the comparison operations to the absolute minimum required set. This allows a backend to expand any arbitrary set of comparisons as long as a minimum set is supported.
      The minimum set of required instructions is ISD::AND, ISD::OR, ISD::SETO(or ISD::SETOEQ) and ISD::SETUO(or ISD::SETUNE). Everything is expanded into one of two patterns:
      Pattern 1: (LHS CC1 RHS) Opc (LHS CC2 RHS)
      Pattern 2: (LHS CC1 LHS) Opc (RHS CC2 RHS)
      
      llvm-svn: 165655
      0242b9b5
    • Michael Liao's avatar
      Add alternative support for FP_ROUND from v2f32 to v2f64 · effae0c8
      Michael Liao authored
      - Due to the current matching vector elements constraints in ISD::FP_EXTEND,
        rounding from v2f32 to v2f64 is scalarized. Add a customized v2f32 widening
        to convert it into a target-specific X86ISD::VFPEXT to work around this
        constraints. This patch also reverts a previous attempt to fix this issue by
        recovering the scalarized ISD::FP_EXTEND pattern and thus significantly
        reduces the overhead of supporting non-power-2 vector FP extend.
      
      llvm-svn: 165625
      effae0c8
    • Stepan Dyatkovskiy's avatar
      Issue description: · f13dbb8e
      Stepan Dyatkovskiy authored
      SchedulerDAGInstrs::buildSchedGraph ignores dependencies between FixedStack
      objects and byval parameters. So loading byval parameters from stack may be
      inserted *before* it will be stored, since these operations are treated as
      independent.
      
      Fix:
      Currently ARMTargetLowering::LowerFormalArguments saves byval registers with
      FixedStack MachinePointerInfo. To fix the problem we need to store byval
      registers with MachinePointerInfo referenced to first the "byval" parameter.
      
      Also commit adds two new fields to the InputArg structure: Function's argument
      index and InputArg's part offset in bytes relative to the start position of
      Function's argument. E.g.: If function's argument is 128 bit width and it was
      splitted onto 32 bit regs, then we got 4 InputArg structs with same arg index,
      but different offset values. 
      
      llvm-svn: 165616
      f13dbb8e
    • Bill Wendling's avatar
      Remove the final bits of Attributes being declared in the Attribute · bbcdf4e2
      Bill Wendling authored
      namespace. Use the attribute's enum value instead. No functionality change
      intended.
      
      llvm-svn: 165610
      bbcdf4e2
    • Lang Hames's avatar
      My earlier "fix" for PBQP (see r165201) was incorrect. The real issue was that · 05fee08d
      Lang Hames authored
      checkRegMaskInterference only initializes the bitmask on the first interference.
      
      This fixes PR14027 and (re)fixes PR13945.
      
      llvm-svn: 165608
      05fee08d
    • Andrew Trick's avatar
      misched: fall-back to a target hook for instr bundles. · c334bd45
      Andrew Trick authored
      llvm-svn: 165606
      c334bd45
    • Andrew Trick's avatar
      misched: Use the TargetSchedModel interface wherever possible. · dd79f0fc
      Andrew Trick authored
      Allows the new machine model to be used for NumMicroOps and OutputLatency.
      
      Allows the HazardRecognizer to be disabled along with itineraries.
      
      llvm-svn: 165603
      dd79f0fc
    • Andrew Trick's avatar
      misched: Add computeInstrLatency to TargetSchedModel. · 780fae8c
      Andrew Trick authored
      llvm-svn: 165566
      780fae8c
    • Andrew Trick's avatar
      misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for... · cfcf5202
      Andrew Trick authored
      misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for external users of TargetSchedule.
      
      llvm-svn: 165564
      cfcf5202
    • Andrew Trick's avatar
      misched: Remove LoopDependencies heuristic. · caf1dc78
      Andrew Trick authored
      This wasn't contributing anything significant to postRA heuristics except compile time (by my measurements) and will be replaced by a more general heuristic for cross-region dependencies within the scheduler itself.
      
      llvm-svn: 165563
      caf1dc78
  7. Oct 09, 2012
    • Bill Wendling's avatar
      Use the attribute enums to query if a parameter has an attribute. · 8ccd6ca1
      Bill Wendling authored
      llvm-svn: 165550
      8ccd6ca1
    • Micah Villmow's avatar
      Add in the first step of the multiple pointer support. This adds in support to... · 89021e47
      Micah Villmow authored
      Add in the first step of the multiple pointer support. This adds in support to the data layout for specifying a per address space pointer size.
      The next step is to update the optimizers to allow them to optimize the different address spaces with this information.
      
      llvm-svn: 165505
      89021e47
    • Bill Wendling's avatar
      Create enums for the different attributes. · c9b22d73
      Bill Wendling authored
      We use the enums to query whether an Attributes object has that attribute. The
      opaque layer is responsible for knowing where that specific attribute is stored.
      
      llvm-svn: 165488
      c9b22d73
    • Eric Christopher's avatar
      Fix up comment to be more clear. · 28611368
      Eric Christopher authored
      llvm-svn: 165463
      28611368
    • Nadav Rotem's avatar
      · 35315fea
      Nadav Rotem authored
      Refactor the AddrMode class out of TLI to its own header file.
      This class is used by LSR and a number of places in the codegen.
      This is the first step in de-coupling LSR from TLI, and creating
      a new interface in between them.
      
      llvm-svn: 165455
      35315fea
    • Jakob Stoklund Olesen's avatar
      Don't crash on extra evil irreducible control flow. · 9d1173a8
      Jakob Stoklund Olesen authored
      When the CFG contains a loop with multiple entry blocks, the traces
      computed by MachineTraceMetrics don't always have the same nice
      properties. Loop back-edges are normally excluded from traces, but
      MachineLoopInfo doesn't recognize loops with multiple entry blocks, so
      those back-edges may be included.
      
      Avoid asserting when that happens by adding an isEarlierInSameTrace()
      function that accurately determines if a dominating block is part of the
      same trace AND is above the currrent block in the trace.
      
      llvm-svn: 165434
      9d1173a8
  8. Oct 08, 2012
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