is trivially rematerializable and integrate it into
TargetInstrInfo::isTriviallyReMaterializable. This way, all places that
need to know whether an instruction is rematerializable will get the
same answer.

This enables the useful parts of the aggressive-remat option by
default -- using AliasAnalysis to determine whether a memory location
is invariant, and removes the questionable parts -- rematting operations
with virtual register inputs that may not be live everywhere.

llvm-svn: 83687

MI->addOperand invalidates references to it's operands, avoid touching
the operand after a new one was added.

llvm-svn: 83249

llvm-svn: 83223

Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.

llvm-svn: 83218

Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string.

llvm-svn: 83215

Use MachineFrameInfo.getPristineRegs() to determine which callee-saved registers are available for anti-dependency breaking. Some cleanup.

llvm-svn: 83208

operands of instructions with these properties while breaking anti-dep.

llvm-svn: 83198

basic blocks that are so long that their size overflows a short.

Also assert that overflow does not happen in the future, as requested by Evan.

This fixes PR4401.

llvm-svn: 83159

Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.

llvm-svn: 83122

llvm-svn: 83007

Fix bug in kill flag updating for post-register-allocation scheduling. When the kill flag of a superreg needs to be cleared because there are one or more subregs live, we instead add implicit-defs of those subregs and leave the kill flag on the superreg. This allows us to end the live-range of the superreg without ending the live-ranges of the subregs.

llvm-svn: 82629

Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes.
Not functionality change yet.

llvm-svn: 82273

llvm-svn: 81112

Create our own block initializer for kill fixups as the scheduling one wasn't doing the right thing.

llvm-svn: 80958

llvm-svn: 80702

llvm-svn: 80621

llvm-svn: 80410

llvm-svn: 80002

llvm-svn: 79836

llvm-svn: 78843

llvm-svn: 78773

in breaking an anti-dependence into a separate function.

llvm-svn: 78767

llvm-svn: 78694

llvm-svn: 78687

llvm-svn: 78634

Post RA scheduler changes. Introduce a hazard recognizer that uses the target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets.

llvm-svn: 78563

llvm-svn: 77754

now that TargetOperandInfo does the heavy lifting.

llvm-svn: 77508

This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").

llvm-svn: 75640

Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.

llvm-svn: 75379

llvm-svn: 70950

register destinations that are tied to source operands.  The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly.  The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).

llvm-svn: 68714

llvm-svn: 66653

scheduled in multiple regions, liveness data used by the
anti-dependence breaker is carried from one region to the next, however
the information reflects the state of the instructions before scheduling.
After scheduling, there may be new live range overlaps. Handle this by
pessimizing the liveness data carried between regions to the point where
it will be conservatively correct now matter how the earlier region is
scheduled. This fixes a miscompilation in 176.gcc with the post-RA
scheduler enabled.

llvm-svn: 66558

instruction index across each part. Instruction indices are used
to make live range queries, and live ranges can extend beyond
scheduling region boundaries.

Refactor the ScheduleDAGSDNodes class some more so that it
doesn't have to worry about this additional information.

llvm-svn: 64288

a scheduling region boundary.  This isn't necessary for
correctness; it helps with compile time, as it avoids the need
for data- and anti-dependencies from all spills and reloads on
the stack-pointer modification.

llvm-svn: 64255

scheduling, and generalize is so that preserves state across
scheduling regions. This fixes incorrect live-range information around
terminators and labels, which are effective region boundaries.

In place of looking for terminators to anchor inter-block dependencies,
introduce special entry and exit scheduling units for this purpose.

llvm-svn: 64254

llvm-svn: 63938

that used this header to select a scheduling policy should
use SchedulerRegistry.h instead (llvm-gcc and clang were
updated a while ago).

llvm-svn: 63934

basic-block segments bottom-up instead of top down. This
is the first step in a general restructuring of the way
register liveness is tracked in the post-RA scheduler.

llvm-svn: 63643