instruction encodings can be excluded during mips16 processing.

This revision fixes the issue raised by Jim Grosbach.

bool hasStandardEncoding() const { return !inMips16Mode(); }

When micromips is added it will be

bool StandardEncoding() const { return !inMips16Mode()&&  !inMicroMipsMode(); }

No additional testing is needed other than to assure that there is no regression
from this patch.

Patch by Reed Kotler.

llvm-svn: 157234

32-bit offset jump tables just use real branch instructions and so aren't
marked as data regions. We were still emitting the .end_data_region
marker though, which assert()ed.

rdar://11499158

llvm-svn: 157221

llvm-svn: 157218

Fix use of an unitialized value in the LegalizeOps expansion for ISD::SUB.  No in-tree targets exercise this path.

Patch by Micah Villmow.

llvm-svn: 157215

t2RSB defined the operand correctly, but tRSBS didn't.

llvm-svn: 157200

llvm-svn: 157197

llvm-svn: 157195

Patch by Jose Fonseca.

llvm-svn: 157191

PR1255 (case ranges: work with ConstantRangesSet instead of ConstantInt) related changes for Execution and Verifier.

llvm-svn: 157183

Allow 256-bit shuffles to still be split even if only half of the shuffle comes from two 128-bit pieces.

llvm-svn: 157175

This helps compile time when the greedy register allocator splits live
ranges in giant functions. Without the bias, we would try to grow
regions through the giant edge bundles, usually to find out that the
region became too big and expensive.

If a live range has many uses in blocks near the giant bundle, the small
negative bias doesn't make a big difference, and we still consider
regions including the giant edge bundle.

Giant edge bundles are usually connected to landing pads or indirect
branches.

llvm-svn: 157174

With physreg joining out of the way, it is easy to recognize the
instructions that need their kill flags cleared while testing for
interference.

This allows us to skip the final scan of all instructions for an 11%
speedup of the coalescer pass.

llvm-svn: 157169

It can sometimes be used in addressing modes that don't support %ESP.

llvm-svn: 157165

It can be necessary to restrict to a sub-class before accessing
sub-registers.

llvm-svn: 157164

When rewriting operands, make sure the new registers have a compatible
register class.

llvm-svn: 157163

may be RAUW'd by the recursive call to LegalizeOps; instead, retrieve
the other operands when calling UpdateNodeOperands.  Fixes PR12889.

llvm-svn: 157162

There should be no difference in the resulting binary, given a sufficiently
smart compiler. However we already had compiler timeouts on the generated
code in Intrinsics.gen, this hopefully makes the lives of slow buildbots a
little easier.

llvm-svn: 157161

Found by valgrind.

llvm-svn: 157160

This seems to fix the remaining compile-time failures on PPC64 when
compiling with -enable-ppc-preinc.

llvm-svn: 157159

llvm-svn: 157155

llvm-svn: 157152

They need to go on the PICLDR as the verifier points out.

llvm-svn: 157151

Not all GR64 registers have sub_8bit sub-registers.

llvm-svn: 157150

X86 has 2-addr instructions with different constraints on the tied def
and use operands. One is GR32, one is GR32_NOSP.

llvm-svn: 157149

llvm-svn: 157148

This function adds copies to be erased to DupCopies, avoid also adding
them to DeadCopies.

llvm-svn: 157147

Avoid looking at the operands of a potentially erased instruction.

llvm-svn: 157146

llvm-svn: 157145

llvm-svn: 157144

That struct ought to be a LiveInterval implementation detail.

llvm-svn: 157143

llvm-svn: 157142

LoopUnswitch.  Fixes PR12887.

llvm-svn: 157140

llvm-svn: 157137

Dead code elimination during coalescing could cause a virtual register
to be split into connected components. The following rewriting would be
confused about the already joined copies present in the code, but
without a corresponding value number in the live range.

Erase all joined copies instantly when joining intervals such that the
MI and LiveInterval representations are always in sync.

llvm-svn: 157135

copied-in constant, as a subsequent user may rely on over alignment.
Fixes PR12885.

llvm-svn: 157134

The current code will generate a prologue which starts with something like:
        mflr 0
        stw 31, -4(1)
        stw 0, 4(1)
        stwu 1, -16(1)

But under the PPC32 SVR4 ABI, access to negative offsets from R1 is not allowed.

This was pointed out by Peter Bergner.

llvm-svn: 157133

Dead code and joined copies are now eliminated on the fly, and there is
no need for a post pass.

This makes the coalescer work like other modern register allocator
passes: Code is changed on the fly, there is no pending list of changes
to be committed.

llvm-svn: 157132

The late dead code elimination is no longer necessary.

The test changes are cause by a register hint that can be either %rdi or
%rax. The choice depends on the use list order, which this patch changes.

llvm-svn: 157131

Before rewriting uses of one value in A to register B, check that there
are no tied uses. That would require multiple A values to be rewritten.

This bug can't bite in the current version of the code for a fairly
subtle reason: A tied use would have caused 2-addr to insert a copy
before the use. If the copy has been coalesced, it will be found by the
same loop changed by this patch, and the optimization is aborted.

This was exposed by 400.perlbench and lua after applying a patch that
deletes joined copies aggressively.

llvm-svn: 157130

llvm-svn: 157129