All the credit goes to Jan Voung for noticing it was dead!

llvm-svn: 166902

Previously mips16 was sharing the pattern addr which is used for mips32
and mips64. This had a number of problems:
1) Storing and loading byte and halfword quantities for mips16 has particular
problems due to the primarily non mips16 nature of SP. When we must
load/store byte/halfword stack objects in a function, we must create a mips16
alias register for SP. This functionality is tested in stchar.ll.
2) We need to have an FP register under certain conditions (such as 
dynamically sized alloca). We use mips16 register S0 for this purpose.
In this case, we also use this register when accessing frame objects so this
issue also affects the complex pattern addr16. This functionality is
tested in alloca16.ll.

The Mips16InstrInfo.td has been updated to use addr16 instead of addr.

The complex pattern C++ function for addr has been copied to addr16 and
updated to reflect the above issues.

llvm-svn: 166897

This fixes PR14194.

llvm-svn: 166880

I don't think this is possible with the current implementation but that may change eventually.

llvm-svn: 166877

This turns loops like
  for (unsigned i = 0; i != n; ++i)
    p[i] = p[i+1];
into memmove, which has a highly optimized implementation in most libcs.

This was really easy with the new DependenceAnalysis :)

llvm-svn: 166875

Requires a lot less code and complexity on loop-idiom's side and the more
precise analysis can catch more cases, like the one I included as a test case.
This also fixes the edge-case miscompilation from PR9481.

Compile time performance seems to be slightly worse, but this is mostly due
to an extra LCSSA run scheduled by the PassManager and should be fixed there.

llvm-svn: 166874

SCEV validator: Ignore CouldNotCompute/undef on both sides. This is mostly noise and blocks finding more severe bugs.

llvm-svn: 166873

llvm-svn: 166872

offer up my email to the spam lords for it. Hopefully this will
eventually be more automatic, but we don't want people to think there is
only one option.

llvm-svn: 166870

The monolithic interface for instruction costs has been split into
several functions. This is the corresponding change. No functionality
change is intended.

llvm-svn: 166865

1. Fix a bug in getTypeConversion. When a *simple* type is split, we need to return the type of the split result.
2. Change the maximum vectorization width from 4 to 8.
3. A test for both.

llvm-svn: 166864

llvm-svn: 166854

llvm-svn: 166852

arguments.

This is rather conservative and should be fixed later to be more aggressive.

llvm-svn: 166851

previous iteration.

llvm-svn: 166850

LowerFormalArguments in MipsTargetLowering.

No functionality change intended.

llvm-svn: 166846

of vararg functions back to the stack.

llvm-svn: 166844

This method emits nodes for passing byval arguments in registers and stack.
This has the same functionality as existing functions PassByValArg64 and
WriteByValArg which will be deleted later.

llvm-svn: 166843

This method copies byval arguments passed in registers onto the stack and has
the same functionality as existing functions CopyMips64ByValRegs and
ReadByValArg which will be deleted later.

llvm-svn: 166841

arguments and inquire about calling convention information.

llvm-svn: 166840

llvm-svn: 166837

Refactor the VectorTargetTransformInfo interface.

Add getCostXXX calls for different families of opcodes, such as casts, arithmetic, cmp, etc.

Port the LoopVectorizer to the new API.

The LoopVectorizer now finds instructions which will remain uniform after vectorization. It uses this information when calculating the cost of these instructions.

llvm-svn: 166836

Keep the integer_insertelement test case, the new coalescer can handle
this kind of lane insertion without help from pseudo-instructions.

llvm-svn: 166835

llvm-svn: 166834

No functional change.

llvm-svn: 166829

Don't pass it around everywhere as a function argument.

llvm-svn: 166828

llvm-svn: 166827

llvm-svn: 166822

llvm-svn: 166821

Don't pass it everywhere as an argument.

llvm-svn: 166820

llvm-svn: 166819

llvm-svn: 166818

It is just as easy to use MRI::isReserved() now.

llvm-svn: 166817

Some instructions in ARM require 2 even-odd paired GPRs. This
patch adds support for such register class.

Patch by Weiming Zhao!

llvm-svn: 166816

No functional change.

llvm-svn: 166814

The new coalescer can already do all of this, so there is no need to
duplicate the efforts.

llvm-svn: 166813

It was unmaintained and not much more than a stub. The new DependenceAnalysis
pass is both more general and complete.

llvm-svn: 166810

llvm-svn: 166804

APInt::shl generated llvm.trap to guard against shifts greater than bit-width.
This was already checked with an assert, and there was a special case for
shifts equal to bit-width. Modify this check to catch shifts greater than or
equal to bit-width, so llvm.trap isn't generated.

Patch contributed by JF Bastien

llvm-svn: 166803

llvm-svn: 166802