No functionality changed. Another step of refactoring toward solving
PR14487.

llvm-svn: 170300

No functionality changed. Refactoring leading up to the fix for PR14478
which requires some significant changes to the memset and memcpy
rewriting.

llvm-svn: 170299

llvm-svn: 170298

llvm-svn: 170297

llvm-svn: 170296

llvm-svn: 170295

llvm-svn: 170294

llvm-svn: 170293

Currently there is no instruction encoding info and
XCoreDisassembler::getInstruction() always returns Fail. I intend to add
instruction encodings and tests in follow on commits.

llvm-svn: 170292

llvm-svn: 170291

llvm-svn: 170290

llvm-svn: 170289

This change adds XCoreMCInstLower to do the lowering to MCInst and
XCoreInstPrinter to print the MCInsts.

llvm-svn: 170288

llvm-svn: 170286

from some other unrelated header.

Patch by Kai.

llvm-svn: 170284

This enables us to use the same document structure as in other files.

llvm-svn: 170283

Don't use SourceLineCache in getColumnNumber if LastLineNoResult is past the end of the cache. Fixes PR14570.

llvm-svn: 170281

llvm-svn: 170280

Mips16 is really a processor decoding mode (ala thumb 1) and in the same
program, mips16 and mips32 functions can exist and can call each other.

If a jal type instruction encounters an address with the lower bit set, then
the processor switches to mips16 mode (if it is not already in it). If the
lower bit is not set, then it switches to mips32 mode.

The linker knows which functions are mips16 and which are mips32.
When relocation is performed on code labels, this lower order bit is
set if the code label is a mips16 code label.

In general this works just fine, however when creating exception handling
tables and dwarf, there are cases where you don't want this lower order
bit added in.

This has been traditionally distinguished in gas assembly source by using a
different syntax for the label.

lab1:      ; this will cause the lower order bit to be added
lab2=.     ; this will not cause the lower order bit to be added

In some cases, it does not matter because in dwarf and debug tables
the difference of two labels is used and in that case the lower order
bits subtract each other out.

To fix this, I have added to mcstreamer the notion of a debuglabel.
The default is for label and debug label to be the same. So calling
EmitLabel and EmitDebugLabel produce the same result.

For various reasons, there is only one set of labels that needs to be
modified for the mips exceptions to work. These are the "$eh_func_beginXXX" 
labels.

Mips overrides the debug label suffix from ":" to "=." .

This initial patch fixes exceptions. More changes most likely
will be needed to DwarfCFException to make all of this work
for actual debugging. These changes will be to emit debug labels in some
places where a simple label is emitted now.

Some historical discussion on this from gcc can be found at:
http://gcc.gnu.org/ml/gcc-patches/2008-08/msg00623.html
http://gcc.gnu.org/ml/gcc-patches/2008-11/msg01273.html 

llvm-svn: 170279

The adornment:

===
Foo
===

is for titles, not sections.

llvm-svn: 170278

highlight console output with "code-block:: console", etc.

llvm-svn: 170276

Patch by Anastasi Voitova with with small fixes by me.

llvm-svn: 170275

[sanitizer] fix a bug that has crept into the sanitizer allocator and caused SEGV on allocations between 1Mb and 2Mb, improve the test

llvm-svn: 170274

We match the pattern "x >= y ? x-y : 0" into "subus x, y" and two special cases
if y is a constant. DAGCombiner canonicalizes those so we first have to undo the
canonicalization for those cases. The pattern occurs in gzip when the loop
vectorizer is enabled. Part of PR14613.

llvm-svn: 170273

heading underline.

llvm-svn: 170272

llvm-svn: 170271

The alloca width is based on the alloc size, not the type size.

llvm-svn: 170270

Not all chips targeted by x86_64 have this feature, but a dramatically
increasing number do. Specifying a chip-specific tuning parameter will
continue to turn the feature on or off as appropriate for that
particular chip, but the generic flag should try to achieve the best
performance on the most widely available hardware. Today, the number of
chips with fast UA access dwarfs those without in the x86-64 space.

Note that this also brings LLVM's code generation for this '-march' flag
more in line with that of modern GCCs. Reviewed by Dan Gohman.

llvm-svn: 170269

llvm-svn: 170268

llvm-svn: 170267

Remove the “len” defaulted parameter from CommandReturnObject::AppendMessage, AppendWarning and AppendError.  Nobody was using them, and it meant if you accidentally used the AppendWarning when you meant AppendWarningWithFormat with an integer in the format string, it would compile and then return your string plus some unknown amount of junk.

llvm-svn: 170266

Memory read's "repeat" behavior forgets "-t" option. It also formatted the type as hex bytes + ASCII. Now we revert to the default format when displaying types unless the user sets the format option manually.

llvm-svn: 170265

x/a print wouldn't always reset the word size to the size of a pointer if a previous memory read using x/<gdb-format> had been used that set it to another width.

llvm-svn: 170264

Results in better block placement that helps close the
performance gap when making ubsan checks recoverable.

llvm-svn: 170263

_regexp_attach doesn't handle the case where no arguments are provided. It now also handles the case you were you pass options.

llvm-svn: 170262

The notes on the objc_method_family and ns_returns_retained-type attributes
have been moved to the Objective-C section, since both are used by ARC.
The notes on analyzer_noreturn are now only on the analyzer site.

The inadequacy of these docs was noticed months ago by Jonathan Sauer;
I'm only just now getting around to cleaning them up.

llvm-svn: 170261

The file still exists in docs/analyzer/, but it won't be linked to from
clang.llvm.org or processed as part of the default Sphinx doc-build.
RegionStore has changed a lot from what Ted and Zhongxing describe here!

llvm-svn: 170260

In this case, essentially it is soft float with different library routines.
The next step will be to make this fully interoperational with mips32 floating
point and that requires creating stubs for functions with signatures that
contain floating point types.

I have a more sophisticated design for mips16 hardfloat which I hope to
implement at a later time that directly does floating point without the need
for function calls.

The mips16 encoding has no floating point instructions so one needs to
switch to mips32 mode to execute floating point instructions.

llvm-svn: 170259

Make emitDIE public accordingly. No functional change.

llvm-svn: 170258

llvm-svn: 170257