Until now all debug info MDNodes referred to a root MDNode, a compile unit. This simplified handling of these needs in dwarf writer.  However, one side effect of this is that during link time optimization all these MDNodes are _not_ uniqued. In other words there will be N number of MDNodes describing "int", "char" and all other types, which would suddenly grow when each object file starts using libraries like STL.

MDNodes graph structure such that compiler unit keeps track of important MDNodes and update dwarf writer to process mdnodes top-down instead of bottom up.

llvm-svn: 137778

The argument is unused, and is a layering violation in any case.

llvm-svn: 137735

llvm-svn: 137728

llvm-svn: 137719

llvm-svn: 137689

llvm-svn: 137683

llvm-svn: 137668

llvm-svn: 137663

There is no need to maintain a set to keep track of variables that use location expressions. In such cases, AT_location attribute's value will be a label.

llvm-svn: 137659

llvm-svn: 137658

llvm-svn: 137656

When a variable is inlined multiple places, abstract variable keeps name, location, type etc.. info and all other concreate instances of the variable directly refers to abstract variable.

llvm-svn: 137637

llvm-svn: 137632

llvm-svn: 137631

llvm-svn: 137621

llvm-svn: 137618

be illegal, even if the requested vector type is legal. Testcase is one of the
disabled ARM tests in the vector-select patch.

llvm-svn: 137562

This implements the 'landingpad' instruction. It's used to indicate that a basic
block is a landing pad. There are several restrictions on its use (see
LangRef.html for more detail). These restrictions allow the exception handling
code to gather the information it needs in a much more sane way.

This patch has the definition, implementation, C interface, parsing, and bitcode
support in it.

llvm-svn: 137501

llvm-svn: 137485

llvm-svn: 137480

llvm-svn: 137478

llvm-svn: 137466

when building with assertions disabled.

llvm-svn: 137460

This is possible now that we now longer provide an interface to iterate
the interference overlaps.

llvm-svn: 137397

llvm-svn: 137381

The Query class now holds two iterators instead of an InterferenceResult
instance. The iterators are used as bookmarks for repeated
collectInterferingVRegs calls.

llvm-svn: 137380

collectInterferingVRegs will be the primary function for interference
checks.

llvm-svn: 137354

No clients are iterating over interference overlaps.

llvm-svn: 137350

The InterferenceResult iterator turned out to be less important than we
thought it would be.  LiveIntervalUnion clients want higher level
information, like the list of interfering virtual registers.

llvm-svn: 137346

llvm-svn: 137321

lower XMM register gets in first. This will allow the SUBREG pattern to
elliminate the first vector insertion. 

llvm-svn: 137310

It's somewhat surprising anything works without this.  Before we would
compile the testcase into:

test:                                   # @test
	movl	$4, 8(%rdi)
	movl	8(%rdi), %eax
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2

now we produce:

test:                                   # @test
	movl	8(%rdi), %eax
	movl	$4, 8(%rdi)
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2
llvm-svn: 137303

llvm-svn: 137283

Distinguish between two copies of one inlined variable. Take 2.

llvm-svn: 137253

While extending definition range of a debug variable, consult lexical scopes also. There is no point extending debug variable out side its lexical block. This provides 6x compile time speedup in some cases.

llvm-svn: 137250

llvm-svn: 137249

llvm-svn: 137246

llvm-svn: 137237

llvm-svn: 137184

Coalescing can remove copy-like instructions with sub-register operands
that constrained the register class.  Examples are:

  x86: GR32_ABCD:sub_8bit_hi -> GR32
  arm: DPR_VFP2:ssub0 -> DPR

Recompute the register class of any virtual registers that are used by
less instructions after coalescing.

This affects code generation for the Cortex-A8 where we use NEON
instructions for f32 operations, c.f. fp_convert.ll:

  vadd.f32  d16, d1, d0
  vcvt.s32.f32  d0, d16

The register allocator is now free to use d16 for the temporary, and
that comes first in the allocation order because it doesn't interfere
with any s-registers.

llvm-svn: 137133