This is common e.g. when doing rip-relative addressing on x86_64.

llvm-svn: 161728

llvm-svn: 161727

llvm-svn: 161726

Add a couple default: llvm_unreachable() to some switch statements. Fix a bad message in an existing llvm_unreachable.

llvm-svn: 161725

FeatureFastUAMem for Nehalem, Westmere and Sandy Bridge.

FeatureFastUAMem is already on if we pass in nehalem or westmere as a command
argument.

rdar: 7252306
llvm-svn: 161717

Detect when there is not enough available ILP, so if-conversion can't
speculate instructions for free.

Compute the lengthening of the critical path when inserting a select
instruction that depends on the condition as well as both sides of the
if.

Reject conversions that would stretch the critical path by more than
half a mispredict penalty.

llvm-svn: 161713

llvm-svn: 161712

Trace::getResourceLength() computes the number of cycles required to
execute the trace when ignoring data dependencies. The number can be
compared to the critical path to estimate the trace ILP.

Trace::getPHIDepth() computes the data dependency depth of a PHI in a
trace successor that isn't necessarily part of the trace.

llvm-svn: 161711

landingpad.  Enforce it in the verifier, and fix the regression tests to match.

llvm-svn: 161697

This change is to be enabled in clang.

rdar://9877866
PR://13350

llvm-svn: 161693

They identify the PHI predecessors in both diamonds and triangles.

llvm-svn: 161689

When a trace ends with a back-edge, include PHIs in the loop header in
the height computations. This makes the critical path through a loop
more accurate by including the latencies of the last instructions in the
loop.

llvm-svn: 161688

- if a boolean test (X86ISD::CMP or X86ISD:SUB) checks a boolean value
  generated from X86ISD::SETCC, try to simplify the boolean value
  generation and checking by reusing the original EFLAGS with proper
  condition code
- add hooks to X86 specific SETCC/BRCOND/CMOV, the major 3 places
  consuming EFLAGS

part of patches fixing PR12312

llvm-svn: 161687

llvm-svn: 161668

llvm-svn: 161664

llvm-svn: 161663

includes both. Deal with feof and ferror potentially being macros.

llvm-svn: 161658

llvm-svn: 161657

Fix crash when when do lto on Bullet.  Dynamic GEPs in SROA were incorrectly being applied to all accesses to an alloca, not just the ones which read from the GEP.  Thanks to Evan for reducing the test.  rdar://11861001

llvm-svn: 161654

When replacing Old with New, it can happen that New is already a
successor. Add the old and new edge weights instead of creating a
duplicate edge.

llvm-svn: 161653

switched from a bytecode+bzip2 to the current bitcode.

llvm-svn: 161651

No changes to these patches, MRI needed to be notified when changing
uses into defs and vice versa.

llvm-svn: 161644

This was the cause of the buildbot failures.

llvm-svn: 161643

This new attribute is intended to be used by the backend to determine how
the inline asm string should be parsed/printed. This patch adds the 
ia_nsdialect attribute and also adds a test case to ensure the IR is
correctly parsed, but there is no functional change at this time.

The standard dialect is assumed to be AT&T.  Therefore, this attribute
should only be added to MS-style inline assembly statements, which use
the Intel dialect.  If we ever support more dialects we'll need to
add additional state to the attribute.

llvm-svn: 161641

These commits broke a number of buildbots.

llvm-svn: 161640

This makes it possible to speed up def_iterator by stopping at the first
use. This makes def_empty() and getUniqueVRegDef() much faster when
there are many uses.

In a +Asserts build, LiveVariables is 100x faster in one case because
getVRegDef() has an assertion that would scan to the end of a
def_iterator chain.

Spill weight calculation is significantly faster (300x in one case)
because isTriviallyReMaterializable() calls MRI->isConstantPhysReg(%RIP)
which calls def_empty(%RIP).

llvm-svn: 161634

Use a more conventional doubly linked list where the Prev pointers form
a cycle. This means it is no longer necessary to adjust the Prev
pointers when reallocating the VRegInfo array.

The test changes are required because the register allocation hint is
using the use-list order to break ties.

llvm-svn: 161633

Register MachineOperands are kept in linked lists accessible via MRI's
reg_iterator interfaces. The linked list management was handled partly
by MachineOperand methods, partly by MRI methods.

Move all of the list management into MRI, delete
MO::AddRegOperandToRegInfo() and MO::RemoveRegOperandFromRegInfo().

Be more explicit about handling the cases where an MRI pointer isn't
available.

llvm-svn: 161632

the register info for getEncodingValue. This builds on the
small patch of yesterday to set HWEncoding in the register
file.

One (deprecated) use was turned into a hard number to avoid
needing register info in the old JIT.

llvm-svn: 161628

No test case, the crash only happens when the default use list order is
changed.

llvm-svn: 161627

llvm-svn: 161626

This new API will be used by clang to parse ms-style inline asms.

One goal of this project is to use this style of inline asm for targets other
then x86.  Therefore, this API needs to be implemented for non-x86 targets at
some point in the future.

llvm-svn: 161624

The fields in the td definition were switched.

llvm-svn: 161607

This patch corrects the definition of umlal/smlal instructions and adds support
for matching them to the ARM dag combiner.

Bug 12213

Patch by Yin Ma!

llvm-svn: 161581

handle the cases where the memory value type was illegal. 
PR 13111. 

llvm-svn: 161565

llvm-svn: 161564

These functions are very generic. There's no reason for them to
be tied to MCObjectWriter.

llvm-svn: 161545

This way of using getNextOperandForReg() was unlikely to work as
intended. We don't give any guarantees about the order of operands in
the use-def chains, so looking only at operands following a given
operand in the chain doesn't make sense.

llvm-svn: 161542

That particular optimization was probably premature anyway.

llvm-svn: 161541

We filter out MachineLoop back-edges during the trace-building PO
traversals, but it is possible to have CFG cycles that aren't natural
loops, and MachineLoopInfo doesn't include such cycles.

Use a standard visited set to detect such CFG cycles, and completely
ignore them when picking traces.

llvm-svn: 161532