Because in CUDA types do not have associated address spaces,
globals are declared in their "native" address space, and accessed
by bitcasting the pointer to address space 0.  This relies on address
space 0 being a unified address space.

llvm-svn: 157167

llvm-svn: 157166

It can sometimes be used in addressing modes that don't support %ESP.

llvm-svn: 157165

It can be necessary to restrict to a sub-class before accessing
sub-registers.

llvm-svn: 157164

When rewriting operands, make sure the new registers have a compatible
register class.

llvm-svn: 157163

may be RAUW'd by the recursive call to LegalizeOps; instead, retrieve
the other operands when calling UpdateNodeOperands.  Fixes PR12889.

llvm-svn: 157162

There should be no difference in the resulting binary, given a sufficiently
smart compiler. However we already had compiler timeouts on the generated
code in Intrinsics.gen, this hopefully makes the lives of slow buildbots a
little easier.

llvm-svn: 157161

Found by valgrind.

llvm-svn: 157160

This seems to fix the remaining compile-time failures on PPC64 when
compiling with -enable-ppc-preinc.

llvm-svn: 157159

llvm-svn: 157158

llvm-svn: 157157

llvm-svn: 157155

llvm-svn: 157154

llvm-svn: 157152

They need to go on the PICLDR as the verifier points out.

llvm-svn: 157151

Not all GR64 registers have sub_8bit sub-registers.

llvm-svn: 157150

X86 has 2-addr instructions with different constraints on the tied def
and use operands. One is GR32, one is GR32_NOSP.

llvm-svn: 157149

llvm-svn: 157148

This function adds copies to be erased to DupCopies, avoid also adding
them to DeadCopies.

llvm-svn: 157147

Avoid looking at the operands of a potentially erased instruction.

llvm-svn: 157146

llvm-svn: 157145

llvm-svn: 157144

That struct ought to be a LiveInterval implementation detail.

llvm-svn: 157143

llvm-svn: 157142

This class is meant to be the primary interface for examining a live
range in the vicinity on a given instruction. It avoids all the messy
dealings with iterators and early clobbers.

This is a more abstract interface to live ranges, hiding the
implementation as a vector of segments.

llvm-svn: 157141

LoopUnswitch.  Fixes PR12887.

llvm-svn: 157140

llvm-svn: 157139

I'm pretty sure we are in fact doing the right thing here, but someone who knows the standard better should double-check that we are in fact supposed to zero out the member in the given testcase.

llvm-svn: 157138

llvm-svn: 157137

Make delegating initializers use a similar codepath to base initializers in dependent contexts.  PR12890.

llvm-svn: 157136

Dead code elimination during coalescing could cause a virtual register
to be split into connected components. The following rewriting would be
confused about the already joined copies present in the code, but
without a corresponding value number in the live range.

Erase all joined copies instantly when joining intervals such that the
MI and LiveInterval representations are always in sync.

llvm-svn: 157135

copied-in constant, as a subsequent user may rely on over alignment.
Fixes PR12885.

llvm-svn: 157134

The current code will generate a prologue which starts with something like:
        mflr 0
        stw 31, -4(1)
        stw 0, 4(1)
        stwu 1, -16(1)

But under the PPC32 SVR4 ABI, access to negative offsets from R1 is not allowed.

This was pointed out by Peter Bergner.

llvm-svn: 157133

Dead code and joined copies are now eliminated on the fly, and there is
no need for a post pass.

This makes the coalescer work like other modern register allocator
passes: Code is changed on the fly, there is no pending list of changes
to be committed.

llvm-svn: 157132

The late dead code elimination is no longer necessary.

The test changes are cause by a register hint that can be either %rdi or
%rax. The choice depends on the use list order, which this patch changes.

llvm-svn: 157131

Before rewriting uses of one value in A to register B, check that there
are no tied uses. That would require multiple A values to be rewritten.

This bug can't bite in the current version of the code for a fairly
subtle reason: A tied use would have caused 2-addr to insert a copy
before the use. If the copy has been coalesced, it will be found by the
same loop changed by this patch, and the optimization is aborted.

This was exposed by 400.perlbench and lua after applying a patch that
deletes joined copies aggressively.

llvm-svn: 157130

llvm-svn: 157129

Revert fix to http://llvm.org/bugs/show_bug.cgi?id=12867 for the reason now included in the code comment.

llvm-svn: 157128

llvm-svn: 157127

clang++ and msvc happily had no problem with it but g++ refuses to compile.

llvm-svn: 157126